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Results:
1-18
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Results: 18
Authors:
SENG YK
ROFAIL SS
Citation: Yk. Seng et Ss. Rofail, DESIGN AND ANALYSIS OF A + -1V CMOS 4-QUADRANT ANALOG MULTIPLIER/, IEE proceedings. Circuits, devices and systems, 145(3), 1998, pp. 148-154
Authors:
SENG YK
ROFAIL SS
Citation: Yk. Seng et Ss. Rofail, A CHARGE-TRAPPING-BASED TECHNIQUE TO DESIGN LOW-VOLTAGE BICMOS LOGIC-CIRCUITS, IEEE journal of solid-state circuits, 33(1), 1998, pp. 164-168
Authors:
LAW CF
YEO KS
ROFAIL SS
Citation: Cf. Law et al., BICMOS LOGIC-CIRCUIT FOR SINGLE-BATTERY OPERATION, Electronics Letters, 34(21), 1998, pp. 2013-2015
Authors:
SENG YK
ROFAIL SS
Citation: Yk. Seng et Ss. Rofail, 1.5V HIGH-SPEED ELECTROSTATIC DISCHARGE FREE BICMOS DIGITAL CIRCUIT, Electronics Letters, 34(13), 1998, pp. 1306-1307
Authors:
ROFAIL SS
SENG YK
SENG SY
Citation: Ss. Rofail et al., DELAY-TIME SENSITIVITY ANALYSIS OF MULTIGENERATION BICMOS DIGITAL CIRCUITS, IEE proceedings. Circuits, devices and systems, 144(2), 1997, pp. 60-67
Authors:
ROFAIL SS
SENG YK
Citation: Ss. Rofail et Yk. Seng, A PRECISE TRANSIENT MODEL FOR DELAYED INPUT BICMOS DIGITAL CIRCUITS, International journal of electronics, 83(4), 1997, pp. 441-454
Authors:
ROFAIL SS
SENG YK
Citation: Ss. Rofail et Yk. Seng, EXPERIMENTALLY-BASED ANALYTICAL MODEL OF DEEP-SUBMICRON LDD PMOSFETS IN A BI-MOS HYBRID-MODE ENVIRONMENT, I.E.E.E. transactions on electron devices, 44(9), 1997, pp. 1473-1482
Authors:
ROFAIL SS
SENG YK
Citation: Ss. Rofail et Yk. Seng, NOVEL LOW-VOLTAGE BICMOS DIGITAL CIRCUITS EMPLOYING A LATERAL P-N-P BJT IN A P-MOS STRUCTURE, IEE proceedings. Circuits, devices and systems, 143(2), 1996, pp. 83-90
Authors:
SENG YK
ROFAIL SS
Citation: Yk. Seng et Ss. Rofail, 1.1V FULL-SWING DOUBLE BOOTSTRAPPED BICMOS LOGIC GATES, IEE proceedings. Circuits, devices and systems, 143(1), 1996, pp. 41-45
Authors:
ROFAIL SS
Citation: Ss. Rofail, LATERAL THINKING TURBO-CHARGES SUBMICRON BICMOS, Electronics world + wireless world, 102(1724), 1996, pp. 537-537
Authors:
ROFAIL SS
SENG YK
Citation: Ss. Rofail et Yk. Seng, NEW COMPLEMENTARY BICMOS DIGITAL GATES FOR LOW-VOLTAGE ENVIRONMENTS, Solid-state electronics, 39(5), 1996, pp. 681-687
BICMOS CIRCUIT OPTIMIZATION TECHNIQUE LINKING CHANNEL WIDTH OF MOS DEVICE TO COLLECTOR DESIGN OF BJT
Authors:
ROFAIL SS
SENG YK
Citation: Ss. Rofail et Yk. Seng, BICMOS CIRCUIT OPTIMIZATION TECHNIQUE LINKING CHANNEL WIDTH OF MOS DEVICE TO COLLECTOR DESIGN OF BJT, Electronics Letters, 32(25), 1996, pp. 2300-2301
Authors:
SENG YK
ROFAIL SS
Citation: Yk. Seng et Ss. Rofail, FULL-SWING HIGH-SPEED CBICMOS DIGITAL CIRCUIT FOR LOW-VOLTAGE APPLICATIONS, IEE proceedings. Circuits, devices and systems, 142(1), 1995, pp. 8-14
Authors:
SENG YK
ROFAIL SS
Citation: Yk. Seng et Ss. Rofail, 1.5V HIGH-SPEED LOW-POWER CMOS CURRENT SENSE AMPLIFIER, Electronics Letters, 31(23), 1995, pp. 1991-1993
Authors:
SENG YK
ROFAIL SS
Citation: Yk. Seng et Ss. Rofail, 1.1V HIGH-SPEED LOW-POWER BICMOS LOGIC-CIRCUIT, Electronics Letters, 31(13), 1995, pp. 1039-1041
Authors:
ROFAIL SS
Citation: Ss. Rofail, LOW-VOLTAGE, LOW-POWER BICMOS DIGITAL CIRCUITS, IEEE journal of solid-state circuits, 29(5), 1994, pp. 572-579
Authors:
ROFAIL SS
ELMASRY MI
Citation: Ss. Rofail et Mi. Elmasry, SCHOTTKY MERGED BICMOS STRUCTURES, IEEE journal of solid-state circuits, 29(3), 1994, pp. 356-361
Authors:
ROFAIL SS
ELMASRY MI
Citation: Ss. Rofail et Mi. Elmasry, ANALYSIS OF LATCHUP AND PARASITIC EFFECTS IN MERGED BICMOS STRUCTURES, IEEE journal of solid-state circuits, 28(12), 1993, pp. 1389-1394
Risultati:
1-18
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