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Results: 1-22 |
Results: 22
PARTITIONING OF HARDWARE-SOFTWARE EMBEDDED SYSTEMS - A METRICS-BASED APPROACH
Authors: BALBONI A FORNACIARI W SCIUTO D
Citation: A. Balboni et al., PARTITIONING OF HARDWARE-SOFTWARE EMBEDDED SYSTEMS - A METRICS-BASED APPROACH, Integrated computer-aided engineering, 5(1), 1998, pp. 39-55
AUTOMATIC-GENERATION OF ERROR CONTROL CODES FOR COMPUTER-APPLICATIONS
Authors: FUMMI F SCIUTO D SILVANO C
Citation: F. Fummi et al., AUTOMATIC-GENERATION OF ERROR CONTROL CODES FOR COMPUTER-APPLICATIONS, IEEE transactions on very large scale integration (VLSI) systems, 6(3), 1998, pp. 502-506
TESTABILITY ANALYSIS AND BEHAVIORAL-TESTING OF THE HOPFIELD NEURAL PARADIGM
Authors: ALIPPI C FUMMI F PIURI V SAMI M SCIUTO D
Citation: C. Alippi et al., TESTABILITY ANALYSIS AND BEHAVIORAL-TESTING OF THE HOPFIELD NEURAL PARADIGM, IEEE transactions on very large scale integration (VLSI) systems, 6(3), 1998, pp. 507-511
POWER ESTIMATION OF EMBEDDED SYSTEMS - A HARDWARE SOFTWARE CODESIGN APPROACH/
Authors: FORNACIARI W GUBIAN P SCIUTO D SILVANO C
Citation: W. Fornaciari et al., POWER ESTIMATION OF EMBEDDED SYSTEMS - A HARDWARE SOFTWARE CODESIGN APPROACH/, IEEE transactions on very large scale integration (VLSI) systems, 6(2), 1998, pp. 266-275
FAULT ANALYSIS FOR NETWORKS WITH CONCURRENT ERROR-DETECTION
Authors: BOLCHINI C SALICE F SCIUTO D
Citation: C. Bolchini et al., FAULT ANALYSIS FOR NETWORKS WITH CONCURRENT ERROR-DETECTION, IEEE design & test of computers, 15(4), 1998, pp. 66-74
CLOCK SKEW REDUCTION IN ASIC LOGIC DESIGN - A METHODOLOGY FOR CLOCK TREE MANAGEMENT
Authors: BALBONI A COSTI C PELLENCIN M QUADRINI A SCIUTO D
Citation: A. Balboni et al., CLOCK SKEW REDUCTION IN ASIC LOGIC DESIGN - A METHODOLOGY FOR CLOCK TREE MANAGEMENT, IEEE transactions on computer-aided design of integrated circuits and systems, 17(4), 1998, pp. 344-356
SPECIAL SECTION ON VHDL
Authors: SCIUTO D
Citation: D. Sciuto, SPECIAL SECTION ON VHDL, Journal of systems architecture, 44(1), 1997, pp. 1-2
A VHDL-BASED APPROACH FOR POWER ESTIMATION OF EMBEDDED SYSTEMS
Authors: FORNACIARI W GUBIAN P SCIUTO D SILVANO C
Citation: W. Fornaciari et al., A VHDL-BASED APPROACH FOR POWER ESTIMATION OF EMBEDDED SYSTEMS, Journal of systems architecture, 44(1), 1997, pp. 37-61
FOREWORD - CONTRIBUTIONS FROM THE INTERNATIONAL-CONFERENCE ON INNOVATIVE SYSTEMS IN SILICON (ISIS-96)
Authors: SCIUTO D TEWKSBURY SK CHAPMAN GH
Citation: D. Sciuto et al., FOREWORD - CONTRIBUTIONS FROM THE INTERNATIONAL-CONFERENCE ON INNOVATIVE SYSTEMS IN SILICON (ISIS-96), IEEE transactions on components, packaging, and manufacturing technology. Part B, Advanced packaging, 20(3), 1997, pp. 298-299
TESTING CORE-BASED SYSTEMS - A SYMBOLIC METHODOLOGY
Authors: FERRANDI F FUMMI F SCIUTO D MACII E PONCINO M
Citation: F. Ferrandi et al., TESTING CORE-BASED SYSTEMS - A SYMBOLIC METHODOLOGY, IEEE design & test of computers, 14(4), 1997, pp. 69-77
A COMPLETE TESTING STRATEGY BASED ON INTERACTING AND HIERARCHICAL FSMS
Authors: FUMMI F SCIUTO D
Citation: F. Fummi et D. Sciuto, A COMPLETE TESTING STRATEGY BASED ON INTERACTING AND HIERARCHICAL FSMS, Integration, 23(1), 1997, pp. 75-93
A 2-LEVEL COSIMULATION ENVIRONMENT
Authors: FORNACIARI W SCIUTO D SALICE F
Citation: W. Fornaciari et al., A 2-LEVEL COSIMULATION ENVIRONMENT, Computer, 30(6), 1997, pp. 109-111
VHDL (VHSIC HARDWARE DESCRIPTION LANGUAGE) - PREFACE
Authors: SCIUTO D
Citation: D. Sciuto, VHDL (VHSIC HARDWARE DESCRIPTION LANGUAGE) - PREFACE, Journal of systems architecture, 42(2), 1996, pp. 95-96
CATHETER PATROLS - A UNIQUE WAY TO REDUCE THE USE OF CONVENIENCE URINARY CATHETERS
Authors: MCLAUGHLIN A SCIUTO D
Citation: A. Mclaughlin et D. Sciuto, CATHETER PATROLS - A UNIQUE WAY TO REDUCE THE USE OF CONVENIENCE URINARY CATHETERS, Geriatric nursing, 17(5), 1996, pp. 240-243
FSMTEST - FUNCTIONAL TEST-GENERATION FOR SEQUENTIAL-CIRCUITS
Authors: BUONANNO G FUMMI F SCIUTO D LOMBARDI F
Citation: G. Buonanno et al., FSMTEST - FUNCTIONAL TEST-GENERATION FOR SEQUENTIAL-CIRCUITS, Integration, 20(3), 1996, pp. 303-325
A WAFER LEVEL TESTABILITY APPROACH BASED ON AN IMPROVED SCAN INSERTION TECHNIQUE
Authors: BOLCHINI C BUONANNO G FERRANDI F SCIUTO D BOMBANA M CAVALLORO P
Citation: C. Bolchini et al., A WAFER LEVEL TESTABILITY APPROACH BASED ON AN IMPROVED SCAN INSERTION TECHNIQUE, IEEE transactions on components, packaging, and manufacturing technology. Part B, Advanced packaging, 18(3), 1995, pp. 438-447
A NEW DFT METHODOLOGY FOR SEQUENTIAL-CIRCUITS
Authors: COSTI C SERRA M SCIUTO D
Citation: C. Costi et al., A NEW DFT METHODOLOGY FOR SEQUENTIAL-CIRCUITS, JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 7(3), 1995, pp. 223-240
TESTABILITY OF ARTIFICIAL NEURAL NETWORKS - A BEHAVIORAL-APPROACH
Authors: PIURI V SAMI M SCIUTO D
Citation: V. Piuri et al., TESTABILITY OF ARTIFICIAL NEURAL NETWORKS - A BEHAVIORAL-APPROACH, JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 6(2), 1995, pp. 179-190
TIES - A TESTABILITY INCREASE EXPERT-SYSTEM FOR VLSI DESIGN
Authors: BUONANNO G FUMMI F SCIUTO D
Citation: G. Buonanno et al., TIES - A TESTABILITY INCREASE EXPERT-SYSTEM FOR VLSI DESIGN, JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 6(2), 1995, pp. 203-217
CONSTRUCTION TECHNIQUES FOR SYSTEMATIC SEC-DED CODES WITH SINGLE BYTEERROR-DETECTION AND PARTIAL CORRECTION CAPABILITY FOR COMPUTER MEMORY-SYSTEMS
Authors: PENZO L SCIUTO D SILVANO C
Citation: L. Penzo et al., CONSTRUCTION TECHNIQUES FOR SYSTEMATIC SEC-DED CODES WITH SINGLE BYTEERROR-DETECTION AND PARTIAL CORRECTION CAPABILITY FOR COMPUTER MEMORY-SYSTEMS, IEEE transactions on information theory, 41(2), 1995, pp. 584-591
INNOVATIVE STRUCTURES FOR CMOS COMBINATIONAL GATES SYNTHESIS
Authors: BUONANNO G SCIUTO D STEFANELLI R
Citation: G. Buonanno et al., INNOVATIVE STRUCTURES FOR CMOS COMBINATIONAL GATES SYNTHESIS, I.E.E.E. transactions on computers, 43(4), 1994, pp. 385-399
FAULT-DETECTION IN TFCMOS DFCMOS COMBINATIONAL GATES
Authors: BUONANNO G LOMBARDI F SCIUTO D SHEN YN
Citation: G. Buonanno et al., FAULT-DETECTION IN TFCMOS DFCMOS COMBINATIONAL GATES, Integration, 15(2), 1993, pp. 201-227
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