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Results: 101-125/208
Authors:
DUTTON RW
KAN EC
Citation: Rw. Dutton et Ec. Kan, HIERARCHICAL PROCESS SIMULATION FOR NANO-ELECTRONICS, VLSI design (Print), 6(1-4), 1998, pp. 385-391
Authors:
KUMAGAI M
YOKOYAMA K
TAZAWA S
Citation: M. Kumagai et al., A COMPOUND SEMICONDUCTOR PROCESS SIMULATOR AND ITS APPLICATION TO MASK DEPENDENT UNDERCUT ETCHING, VLSI design (Print), 6(1-4), 1998, pp. 393-397
Authors:
GOBBERT MK
CALE TS
RINGHOFER CA
Citation: Mk. Gobbert et al., THE COMBINATION OF EQUIPMENT SCALE AND FEATURE SCALE MODELS FOR CHEMICAL-VAPOR-DEPOSITION VIA A HOMOGENIZATION TECHNIQUE, VLSI design (Print), 6(1-4), 1998, pp. 399-403
Authors:
PAMULA VK
VENKAT R
Citation: Vk. Pamula et R. Venkat, BEATING IN THE RHEED INTENSITY OSCILLATIONS DURING SURFACTANT-MEDIATED GAAS MOLECULAR-BEAM EPITAXY - PROCESS PHYSICS AND MODELING, VLSI design (Print), 6(1-4), 1998, pp. 405-408
Authors:
MEYYAPPAN M
GOVINDAN TR
Citation: M. Meyyappan et Tr. Govindan, PLASMA PROCESS MODELING FOR INTEGRATED-CIRCUITS MANUFACTURING, VLSI design (Print), 6(1-4), 1998, pp. 409-412
Authors:
LALA PK
Citation: Pk. Lala, SPECIAL ISSUE - VLSI DESIGN ON SELF-CHECKING SYSTEMS - GUEST EDITORIAL, VLSI design, 5(4), 1998, pp. 1-2
Authors:
KARPOVSKY MG
Citation: Mg. Karpovsky, INTEGRATED ONLINE AND OFF-LINE ERROR-DETECTION MECHANISMS IN THE CODING THEORY FRAMEWORK, VLSI design, 5(4), 1998, pp. 313-331
Authors:
MOROSOW A
SAPOSHNIKOV VV
SAPOSHNIKOV VV
GOESSEL N
Citation: A. Morosow et al., SELF-CHECKING COMBINATIONAL-CIRCUITS WITH UNIDIRECTIONALLY INDEPENDENT OUTPUTS, VLSI design, 5(4), 1998, pp. 333-345
Authors:
TARNICK S
Citation: S. Tarnick, EMBEDDED PARITY AND 2-RAIL TSC CHECKERS WITH ERROR-MEMORIZING CAPABILITY, VLSI design, 5(4), 1998, pp. 347-356
Authors:
SHIEH YR
WU CW
Citation: Yr. Shieh et Cw. Wu, DESIGN OF CMOS PSCD CIRCUITS AND CHECKERS FOR STUCK-AT AND STUCK-ON FAULTS, VLSI design, 5(4), 1998, pp. 357-372
Authors:
LO JC
Citation: Jc. Lo, A CASE-STUDY OF SELF-CHECKING CIRCUITS RELIABILITY, VLSI design, 5(4), 1998, pp. 373-383
Authors:
VAINSTEIN FS
Citation: Fs. Vainstein, SELF-CHECKING DESIGN TECHNIQUE FOR NUMERICAL COMPUTATIONS, VLSI design, 5(4), 1998, pp. 385-392
Authors:
MAKKI RZ
Citation: Rz. Makki, GUEST EDITORIAL - ADVANCEMENTS IN POWER-SUPPLY CURRENT TESTING, VLSI design, 5(3), 1997, pp. 1-2
Authors:
ALQUTAYRI MA
SHEPHERD PR
Citation: Ma. Alqutayri et Pr. Shepherd, APPLICATION OF DYNAMIC SUPPLY CURRENT MONITORING TO TESTING MIXED-SIGNAL CIRCUITS, VLSI design, 5(3), 1997, pp. 223-240
Authors:
ISERN E
FIGUERAS J
Citation: E. Isern et J. Figueras, I-DDQ DETECTABLE BRIDGES IN COMBINATIONAL CMOS CIRCUITS, VLSI design, 5(3), 1997, pp. 241-252
Authors:
TOUKMAJI A
HELMS R
MAKKI R
MIKHAIL W
TOOLE P
Citation: A. Toukmaji et al., I-DDQ TESTING EXPERIMENTS FOR VARIOUS CMOS LOGIC DESIGN STRUCTURES, VLSI design, 5(3), 1997, pp. 253-271
Authors:
CHAMPAC VH
FIGUERAS J
Citation: Vh. Champac et J. Figueras, CURRENT TESTING OF CMOS COMBINATIONAL-CIRCUITS WITH SINGLE FLOATING-GATE DEFECTS, VLSI design, 5(3), 1997, pp. 273-284
Authors:
MENON SM
MALAIYA YK
JAYASUMANA AP
TONG CQ
Citation: Sm. Menon et al., OPERATIONAL AND TEST-PERFORMANCE IN THE PRESENCE OF BUILT-IN CURRENT SENSORS, VLSI design, 5(3), 1997, pp. 285-298
Authors:
HWANG S
RAJSUMAN R
Citation: S. Hwang et R. Rajsuman, VLSI TESTING FOR HIGH-RELIABILITY - MIXING I-DDQ TESTING WITH LOGIC TESTING, VLSI design, 5(3), 1997, pp. 299-311
Authors:
KURDAHI FJ
Citation: Fj. Kurdahi, LINKING BEHAVIORAL, STRUCTURAL, AND PHYSICAL MODELS OF HARDWARE, VLSI design, 5(2), 1997, pp. 1-2
Authors:
PEDRAM M
BHAT N
KUH ES
Citation: M. Pedram et al., COMBINING TECHNOLOGY MAPPING WITH LAYOUT, VLSI design, 5(2), 1997, pp. 111-124
Authors:
CHANDRASEKHAR MS
MCCHARLES RH
WALLACE DE
Citation: Ms. Chandrasekhar et al., EFFECTIVE COUPLING BETWEEN LOGIC SYNTHESIS AND LAYOUT TOOLS FOR SYNTHESIS OF AREA AND SPEED-EFFICIENT CIRCUITS, VLSI design, 5(2), 1997, pp. 125-140
Authors:
TYAGI A
Citation: A. Tyagi, STATISTICAL MODULE LEVEL AREA AND DELAY ESTIMATION, VLSI design, 5(2), 1997, pp. 141-153
Authors:
DUTT ND
JHA PK
Citation: Nd. Dutt et Pk. Jha, RT COMPONENT SETS FOR HIGH-LEVEL DESIGN APPLICATIONS, VLSI design, 5(2), 1997, pp. 155-165
Authors:
HARRIS IG
ORAILOGLU A
Citation: Ig. Harris et A. Orailoglu, MODULE SELECTION IN MICROARCHITECTURAL SYNTHESIS FOR MULTIPLE CRITICAL CONSTRAINT SATISFACTION, VLSI design, 5(2), 1997, pp. 167-182