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Table of contents of journal: *IEE proceedings. Computers and digital techniques

Results: 51-75/453
Multiparty key agreement protocols
Authors: Pieprzyk, J Li, CH
Citation: J. Pieprzyk et Ch. Li, Multiparty key agreement protocols, IEE P-COM D, 147(4), 2000, pp. 229-236
Identification of T-codes with minimal average synchronisation delay
Authors: Fong, ACM Higgie, GR
Citation: Acm. Fong et Gr. Higgie, Identification of T-codes with minimal average synchronisation delay, IEE P-COM D, 147(4), 2000, pp. 237-240
Modified Jacobi sequences
Authors: Green, DH Green, PR
Citation: Dh. Green et Pr. Green, Modified Jacobi sequences, IEE P-COM D, 147(4), 2000, pp. 241-251
Fast BBS-sequence generation using Montgomery multiplication
Authors: Parker, MG Kemp, AH Shepherd, SJ
Citation: Mg. Parker et al., Fast BBS-sequence generation using Montgomery multiplication, IEE P-COM D, 147(4), 2000, pp. 252-254
Analysing and reducing the protocol overheads of MPOA in the intra-IASG communication
Authors: Lai, WK Chung, JM
Citation: Wk. Lai et Jm. Chung, Analysing and reducing the protocol overheads of MPOA in the intra-IASG communication, IEE P-COM D, 147(4), 2000, pp. 255-262
An efficient algorithm for computing the Luc chain
Authors: Chiou, SY Laih, CS
Citation: Sy. Chiou et Cs. Laih, An efficient algorithm for computing the Luc chain, IEE P-COM D, 147(4), 2000, pp. 263-265
Integrated fault-tolerant multicast and anycast routing algorithms
Authors: Jia, W Xu, G Zhao, W
Citation: W. Jia et al., Integrated fault-tolerant multicast and anycast routing algorithms, IEE P-COM D, 147(4), 2000, pp. 266-274
Design of fast high-radix SRT dividers and their VLSI implementation
Authors: Wey, CL
Citation: Cl. Wey, Design of fast high-radix SRT dividers and their VLSI implementation, IEE P-COM D, 147(4), 2000, pp. 275-281
RNS-based logarithmic adder
Authors: Preethy, AP Radhakrishnan, D
Citation: Ap. Preethy et D. Radhakrishnan, RNS-based logarithmic adder, IEE P-COM D, 147(4), 2000, pp. 283-287
Low power architecture for floating paint MAC fusion
Authors: Pillai, RVK Al-Khalili, D Al-Khalili, AJ
Citation: Rvk. Pillai et al., Low power architecture for floating paint MAC fusion, IEE P-COM D, 147(4), 2000, pp. 288-296
Design of a unified arithmetic processor based on redundant constant-factor CORDIC with merged scaling operation
Authors: Hsiao, SF Lau, CY
Citation: Sf. Hsiao et Cy. Lau, Design of a unified arithmetic processor based on redundant constant-factor CORDIC with merged scaling operation, IEE P-COM D, 147(4), 2000, pp. 297-303
Reconfigurable systems
Authors: Brebner, G Hutchings, B
Citation: G. Brebner et B. Hutchings, Reconfigurable systems, IEE P-COM D, 147(3), 2000, pp. 133-134
FPGA-based SAT solver architecture with near-zero synthesis and layout overhead
Authors: Zhong, P Martonosi, M Ashar, P
Citation: P. Zhong et al., FPGA-based SAT solver architecture with near-zero synthesis and layout overhead, IEE P-COM D, 147(3), 2000, pp. 135-141
Core-based design methodology for reconfigurable computing applications
Authors: James-Roxby, P Cerro-Prada, E Charlwood, S
Citation: P. James-roxby et al., Core-based design methodology for reconfigurable computing applications, IEE P-COM D, 147(3), 2000, pp. 142-146
Framework and tools for run-time reconfigurable designs
Authors: Shirazi, N Luk, W Cheung, PYK
Citation: N. Shirazi et al., Framework and tools for run-time reconfigurable designs, IEE P-COM D, 147(3), 2000, pp. 147-152
Object oriented development method for reconfigurable embedded systems
Authors: Green, PN Edwards, MD
Citation: Pn. Green et Md. Edwards, Object oriented development method for reconfigurable embedded systems, IEE P-COM D, 147(3), 2000, pp. 153-158
Synthesis of interfaces and communication in reconfigurable embedded systems
Authors: Eisenring, M Platzner, M
Citation: M. Eisenring et M. Platzner, Synthesis of interfaces and communication in reconfigurable embedded systems, IEE P-COM D, 147(3), 2000, pp. 159-165
Power optimisation of FPGA-based designs without rewiring
Authors: Kumthekar, B Benini, L Macii, E Somenzi, F
Citation: B. Kumthekar et al., Power optimisation of FPGA-based designs without rewiring, IEE P-COM D, 147(3), 2000, pp. 167-174
Methods of exploiting simulation technology for simulating the timing of dynamically reconfigurable logic
Authors: Robinson, D Lysaght, P
Citation: D. Robinson et P. Lysaght, Methods of exploiting simulation technology for simulating the timing of dynamically reconfigurable logic, IEE P-COM D, 147(3), 2000, pp. 175-180
Dynamic scheduling of tasks on partially reconfigurable FPGAs
Authors: Diessel, O ElGindy, H Middendorf, M Schmeck, H Schmidt, B
Citation: O. Diessel et al., Dynamic scheduling of tasks on partially reconfigurable FPGAs, IEE P-COM D, 147(3), 2000, pp. 181-188
SiGeHBT BiCMOS FPGAs for fast reconfigurable computing
Authors: Goda, BS McDonald, JF Carlough, SR Krawczyk, TW Kraft, RP
Citation: Bs. Goda et al., SiGeHBT BiCMOS FPGAs for fast reconfigurable computing, IEE P-COM D, 147(3), 2000, pp. 189-194
High-speed interconnect schemes for a pipelined FPGA
Authors: Lee, HJ Flynn, MJ
Citation: Hj. Lee et Mj. Flynn, High-speed interconnect schemes for a pipelined FPGA, IEE P-COM D, 147(3), 2000, pp. 195-202
Reconfigurable analogue systems: The pulse-based approach
Authors: Hamilton, A Papathanasiou, K
Citation: A. Hamilton et K. Papathanasiou, Reconfigurable analogue systems: The pulse-based approach, IEE P-COM D, 147(3), 2000, pp. 203-207
Multi-level logic optimisation based on permissible perturbations
Authors: Zemva, A Trost, A Zajc, B
Citation: A. Zemva et al., Multi-level logic optimisation based on permissible perturbations, IEE P-COM D, 147(2), 2000, pp. 53-58
Heuristics in the routing algorithm for circuit layout design
Authors: Mani, N Quach, NH
Citation: N. Mani et Nh. Quach, Heuristics in the routing algorithm for circuit layout design, IEE P-COM D, 147(2), 2000, pp. 59-64
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