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Results: 1-19 |
Results: 19
A GLOBAL DESCRIPTION OF THE BASE CURRENT 1 F NOISE OF POLYSILICON EMITTER BIPOLAR-TRANSISTORS BEFORE AND AFTER HOT-CARRIER STRESS/
Authors: SIMOEN E DECOUTERE S CLAEYS C DEFERM L
Citation: E. Simoen et al., A GLOBAL DESCRIPTION OF THE BASE CURRENT 1 F NOISE OF POLYSILICON EMITTER BIPOLAR-TRANSISTORS BEFORE AND AFTER HOT-CARRIER STRESS/, Solid-state electronics, 42(9), 1998, pp. 1679-1687
A COMPREHENSIVE CLOSED-FORM MODEL FOR THE QUANTIZED ACCUMULATION LAYER IN MOS STRUCTURES
Authors: KOLDYAEV VI VANDENBOSCH G DEFERM L
Citation: Vi. Koldyaev et al., A COMPREHENSIVE CLOSED-FORM MODEL FOR THE QUANTIZED ACCUMULATION LAYER IN MOS STRUCTURES, Solid-state electronics, 42(1), 1998, pp. 49-56
IMPACT OF THE TRANSMISSION-LINE PROPERTIES OF A METAL ULTRATHIN SILICON DIOXIDE SEMICONDUCTOR FIELD-EFFECT TRANSISTOR ON THE EXTRACTED INVERSION-LAYER THICKNESS
Authors: KOLDYAEV VI CLERIX A DEFERM L VANOVERSTRAETEN R
Citation: Vi. Koldyaev et al., IMPACT OF THE TRANSMISSION-LINE PROPERTIES OF A METAL ULTRATHIN SILICON DIOXIDE SEMICONDUCTOR FIELD-EFFECT TRANSISTOR ON THE EXTRACTED INVERSION-LAYER THICKNESS, Journal of applied physics, 83(4), 1998, pp. 2131-2138
READ-DISTURB AND ENDURANCE OF SSI-FLASH E(2)PROM DEVICES AT HIGH OPERATING TEMPERATURES
Authors: DEBLAUWE J WELLEKENS D GROESENEKEN G HASPESLAGH L VANHOUDT J DEFERM L MAES HE
Citation: J. Deblauwe et al., READ-DISTURB AND ENDURANCE OF SSI-FLASH E(2)PROM DEVICES AT HIGH OPERATING TEMPERATURES, I.E.E.E. transactions on electron devices, 45(12), 1998, pp. 2466-2474
OPTIMIZATION OF POLYSILICON ENCAPSULATED LOCAL OXIDATION OF SILICON -CAVITY DIMENSION EFFECTS ON MECHANICAL-STRESS AND GATE OXIDE INTEGRITY
Authors: BADENES G ROOYACKERS R JONES SK BAZLEY D BEANLAND R DEWOLF I DEFERM L
Citation: G. Badenes et al., OPTIMIZATION OF POLYSILICON ENCAPSULATED LOCAL OXIDATION OF SILICON -CAVITY DIMENSION EFFECTS ON MECHANICAL-STRESS AND GATE OXIDE INTEGRITY, Journal of the Electrochemical Society, 145(5), 1998, pp. 1653-1659
POLYSILICON ENCAPSULATED LOCAL OXIDATION OF SILICON FOR DEEP-SUBMICRON LATERAL ISOLATION
Authors: BADENES G ROOYACKERS R DEWOLF I DEFERM L
Citation: G. Badenes et al., POLYSILICON ENCAPSULATED LOCAL OXIDATION OF SILICON FOR DEEP-SUBMICRON LATERAL ISOLATION, JPN J A P 1, 36(3B), 1997, pp. 1325-1329
VOLTAGE VARIANT SOURCE SIDE INJECTION FOR MULTILEVEL CHARGE STORAGE IN FLASH EEPROM
Authors: MONTANARI D VANHOUDT J WELLEKENS D VANHOREBEEK G HASPESLAGH L DEFERM L GROESENEKEN G MAES HE
Citation: D. Montanari et al., VOLTAGE VARIANT SOURCE SIDE INJECTION FOR MULTILEVEL CHARGE STORAGE IN FLASH EEPROM, IEEE transactions on components, packaging, and manufacturing technology. Part A, 20(2), 1997, pp. 196-202
SUBSTRATE BONDING TECHNIQUES FOR CMOS PROCESSED WAFERS
Authors: VANDERGROEN S ROSMEULEN M BAERT K JANSEN P DEFERM L
Citation: S. Vandergroen et al., SUBSTRATE BONDING TECHNIQUES FOR CMOS PROCESSED WAFERS, Journal of micromechanics and microengineering, 7(3), 1997, pp. 108-110
MODELING THE SUBTHRESHOLD SWING IN MOSFETS
Authors: VANDAMME EP JANSEN P DEFERM L
Citation: Ep. Vandamme et al., MODELING THE SUBTHRESHOLD SWING IN MOSFETS, IEEE electron device letters, 18(8), 1997, pp. 369-371
IMPORTANCE OF DETERMINING THE POLYSILICON DOPANT PROFILE DURING PROCESS-DEVELOPMENT
Authors: DEBUSSCHERE I DEFERM L VANDERVORST W
Citation: I. Debusschere et al., IMPORTANCE OF DETERMINING THE POLYSILICON DOPANT PROFILE DURING PROCESS-DEVELOPMENT, Journal of vacuum science & technology. B, Microelectronics and nanometer structures processing, measurement and phenomena, 14(1), 1996, pp. 265-271
ON THE OPTIMIZATION OF OUTSIDE SPACER BIPOLAR-TRANSISTORS FOR 0.5-MU-M HIGH-PERFORMANCE MIXED ANALOG DIGITAL BICMOS/
Authors: CUTHBERTSON A DECOUTERE S DEFERM L
Citation: A. Cuthbertson et al., ON THE OPTIMIZATION OF OUTSIDE SPACER BIPOLAR-TRANSISTORS FOR 0.5-MU-M HIGH-PERFORMANCE MIXED ANALOG DIGITAL BICMOS/, Electrical engineering, 79(5), 1996, pp. 343-351
PERFORMANCE AND RELIABILITY ASPECTS OF FOND - A NEW DEEP-SUBMICRON CMOS DEVICE CONCEPT
Authors: BELLENS R VANDENBOSCH G HABAS P MIEVILLE JP BADENES G CLERIX A GROESENEKEN G DEFERM L MAES HE
Citation: R. Bellens et al., PERFORMANCE AND RELIABILITY ASPECTS OF FOND - A NEW DEEP-SUBMICRON CMOS DEVICE CONCEPT, I.E.E.E. transactions on electron devices, 43(9), 1996, pp. 1407-1415
IMPACT OF POLYSILICON EMITTER INTERFACIAL LAYER ENGINEERING ON THE 1 F NOISE OF BIPOLAR-TRANSISTORS/
Authors: SIMOEN E DECOUTERE S CUTHBERTSON A CLAEYS CL DEFERM L
Citation: E. Simoen et al., IMPACT OF POLYSILICON EMITTER INTERFACIAL LAYER ENGINEERING ON THE 1 F NOISE OF BIPOLAR-TRANSISTORS/, I.E.E.E. transactions on electron devices, 43(12), 1996, pp. 2261-2268
STUDY OF THE HOT-CARRIER DEGRADATION PERFORMANCE OF 0.35-MU-M FULLY OVERLAPPED LDD-DEVICES
Authors: BELLENS R HABAS P GROESENEKEN G MAES HE MIEVILLE JP VANDENBOSCH G DEFERM L
Citation: R. Bellens et al., STUDY OF THE HOT-CARRIER DEGRADATION PERFORMANCE OF 0.35-MU-M FULLY OVERLAPPED LDD-DEVICES, Microelectronic engineering, 28(1-4), 1995, pp. 265-268
A NEW METHOD FOR MEASURING THE SATURATION VELOCITY OF SUBMICRON CMOS TRANSISTORS
Authors: SCHREUTELKAMP RJ DEFERM L
Citation: Rj. Schreutelkamp et L. Deferm, A NEW METHOD FOR MEASURING THE SATURATION VELOCITY OF SUBMICRON CMOS TRANSISTORS, Solid-state electronics, 38(4), 1995, pp. 791-793
INVESTIGATION OF THE HIGH-FREQUENCY NOISE-FIGURE REDUCTION OF SIGE HETEROJUNCTION BIPOLAR-TRANSISTORS USING ACTUALISED PHYSICAL MODELS
Authors: DECOUTERE S POORTMANS J DEFERM L NIJS J
Citation: S. Decoutere et al., INVESTIGATION OF THE HIGH-FREQUENCY NOISE-FIGURE REDUCTION OF SIGE HETEROJUNCTION BIPOLAR-TRANSISTORS USING ACTUALISED PHYSICAL MODELS, Solid-state electronics, 38(1), 1995, pp. 157-162
SERIES RESISTANCE EFFECTS IN SUBMICRON MOS-TRANSISTORS OPERATED FROM 300-K DOWN TO 4.2-K
Authors: GUTIERREZ EA DEFERM L DECLERCK G
Citation: Ea. Gutierrez et al., SERIES RESISTANCE EFFECTS IN SUBMICRON MOS-TRANSISTORS OPERATED FROM 300-K DOWN TO 4.2-K, Journal de physique. IV, 4(C6), 1994, pp. 31-36
A 5 V-COMPATIBLE FLASH EEPROM CELL WITH MICROSECOND PROGRAMMING TIME FOR EMBEDDED MEMORY APPLICATIONS
Authors: VANHOUDT J WELLEKENS D FARAONE L HASPESLAGH L DEFERM L GROESENEKEN G MAES HE
Citation: J. Vanhoudt et al., A 5 V-COMPATIBLE FLASH EEPROM CELL WITH MICROSECOND PROGRAMMING TIME FOR EMBEDDED MEMORY APPLICATIONS, IEEE transactions on components, packaging, and manufacturing technology. Part A, 17(3), 1994, pp. 380-389
HIMOS - A HIGH EFFICENCY FLASH E(2)PROM CELL FOR EMBEDDED MEMORY APPLICATIONS
Authors: VANHOUDT J HASPESLAGH L WELLEKENS D DEFERM L GROESENEKEN G MAES HE
Citation: J. Vanhoudt et al., HIMOS - A HIGH EFFICENCY FLASH E(2)PROM CELL FOR EMBEDDED MEMORY APPLICATIONS, I.E.E.E. transactions on electron devices, 40(12), 1993, pp. 2255-2263
Risultati: 1-19 |