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Results: 1-13 |
Results: 13
Parallel, pipelined and folded architectures for computation of 1-D and 2-D DCT in image and video codec
Authors: Hsiao, SF Tseng, JM
Citation: Sf. Hsiao et Jm. Tseng, Parallel, pipelined and folded architectures for computation of 1-D and 2-D DCT in image and video codec, J VLSI S P, 28(3), 2001, pp. 205-220
A new hardware-efficient algorithm and architecture for computation of 2-DDCTs on a linear array
Authors: Hsiao, SF Shiue, WR
Citation: Sf. Hsiao et Wr. Shiue, A new hardware-efficient algorithm and architecture for computation of 2-DDCTs on a linear array, IEEE CIR SV, 11(11), 2001, pp. 1149-1159
Knee muscle isometric strength, voluntary activation and antagonist co-contraction in the first six months after stroke
Authors: Newham, DJ Hsiao, SF
Citation: Dj. Newham et Sf. Hsiao, Knee muscle isometric strength, voluntary activation and antagonist co-contraction in the first six months after stroke, DISABIL REH, 23(9), 2001, pp. 379-386
Predicting long-term care institution utilization among post-rehabilitation stroke patients in Taiwan: a medical centre-based study
Authors: Lin, JH Hsieh, CL Hsiao, SF Huang, MH
Citation: Jh. Lin et al., Predicting long-term care institution utilization among post-rehabilitation stroke patients in Taiwan: a medical centre-based study, DISABIL REH, 23(16), 2001, pp. 722-730
Redundant constant-factor implementation of multi-dimensional CORDIC and its application to complex SVD
Authors: Hsiao, SF Lau, CY Delosme, JM
Citation: Sf. Hsiao et al., Redundant constant-factor implementation of multi-dimensional CORDIC and its application to complex SVD, J VLSI S P, 25(2), 2000, pp. 155-166
Design and implementation of a novel linear-array DCT/IDCT processor with complexity of order log(2) N
Authors: Hsiao, SF Shiue, WR Tseng, JM
Citation: Sf. Hsiao et al., Design and implementation of a novel linear-array DCT/IDCT processor with complexity of order log(2) N, IEE P-VIS I, 147(5), 2000, pp. 400-408
Design of a unified arithmetic processor based on redundant constant-factor CORDIC with merged scaling operation
Authors: Hsiao, SF Lau, CY
Citation: Sf. Hsiao et Cy. Lau, Design of a unified arithmetic processor based on redundant constant-factor CORDIC with merged scaling operation, IEE P-COM D, 147(4), 2000, pp. 297-303
Efficient synthesiser for generation of fast parallel multipliers
Authors: Hsiao, SF Jiang, MR
Citation: Sf. Hsiao et Mr. Jiang, Efficient synthesiser for generation of fast parallel multipliers, IEE P-COM D, 147(1), 2000, pp. 49-52
Design of low-cost and high-throughput linear arrays for DFT computations:Algorithms, architectures, and implementations
Authors: Hsiao, SF Shiue, WR
Citation: Sf. Hsiao et Wr. Shiue, Design of low-cost and high-throughput linear arrays for DFT computations:Algorithms, architectures, and implementations, IEEE CIR-II, 47(11), 2000, pp. 1188-1203
VLSI design of an efficient embedded zerotree wavelet coder with function of digital watermarking
Authors: Hsiao, SF Tai, YC Chang, KH
Citation: Sf. Hsiao et al., VLSI design of an efficient embedded zerotree wavelet coder with function of digital watermarking, IEEE CONS E, 46(3), 2000, pp. 628-636
Alberta infant motor scale: Reliability and validity when used on preterm infants in Taiwan
Authors: Jeng, SF Yau, KIT Chen, LC Hsiao, SF
Citation: Sf. Jeng et al., Alberta infant motor scale: Reliability and validity when used on preterm infants in Taiwan, PHYS THER, 80(2), 2000, pp. 168-178
A cost-efficient and fully-pipelinable architecture for DCT/IDCT
Authors: Hsiao, SF Shiue, WR Tseng, JM
Citation: Sf. Hsiao et al., A cost-efficient and fully-pipelinable architecture for DCT/IDCT, IEEE CONS E, 45(3), 1999, pp. 515-525
Design, implementation and analysis of a new redundant CORDIC processor with constant scaling factor and regular structure
Authors: Hsiao, SF Chen, JY
Citation: Sf. Hsiao et Jy. Chen, Design, implementation and analysis of a new redundant CORDIC processor with constant scaling factor and regular structure, J VLSI S P, 20(3), 1998, pp. 267-278
Risultati: 1-13 |