AAAAAA

   
Results: 1-17 |
Results: 17
Electrical properties of ultrathin oxide grown by high pressure oxidation and N2O nitridation for ULSI device applications
Authors: Roh, TM Lee, DW Kim, J Koo, JG Nam, KS Lee, DD
Citation: Tm. Roh et al., Electrical properties of ultrathin oxide grown by high pressure oxidation and N2O nitridation for ULSI device applications, INT J ELECT, 88(4), 2001, pp. 423-434
High-voltage power integrated circuit technology using SOI for driving plasma display panels
Authors: Kim, J Roh, TM Kim, SG Song, QS Lee, DW Koo, JG Cho, KI Ma, DS
Citation: J. Kim et al., High-voltage power integrated circuit technology using SOI for driving plasma display panels, IEEE DEVICE, 48(6), 2001, pp. 1256-1263
Trench formation and filling technique for dielectric isolation of plasma display panel driver integrated circuits
Authors: Kim, SG Kim, J Koo, JG Nam, KS Cho, KI Bae, IH
Citation: Sg. Kim et al., Trench formation and filling technique for dielectric isolation of plasma display panel driver integrated circuits, J VAC SCI B, 18(5), 2000, pp. 2482-2485
A novel simplified process for fabricating a very high density P-channel trench gate power MOSFET
Authors: Nam, KS Lee, JW Kim, SG Roh, TM Park, HS Koo, JG Cho, KI
Citation: Ks. Nam et al., A novel simplified process for fabricating a very high density P-channel trench gate power MOSFET, IEEE ELEC D, 21(7), 2000, pp. 365-367
Highly reliable trench DMOSFET realized by using trench corner rounding
Authors: Kim, SG Kim, J Koo, JG Nam, KS Cho, KI Lee, JW Son, JS
Citation: Sg. Kim et al., Highly reliable trench DMOSFET realized by using trench corner rounding, J KOR PHYS, 37(6), 2000, pp. 882-885
High-voltage SOI power IC technology with non-RESURF n-LDMOSFET and RESURFp-LDMOSFET for PDP scan-driver applications
Authors: Roh, TM Lee, DW Kim, J Kim, SG Song, QS Kang, JY Koo, JG Nam, KS Cho, KI
Citation: Tm. Roh et al., High-voltage SOI power IC technology with non-RESURF n-LDMOSFET and RESURFp-LDMOSFET for PDP scan-driver applications, J KOR PHYS, 37(6), 2000, pp. 889-892
Structural modification of a trench by hydrogen annealing
Authors: Lee, JW Lee, JY Kim, SG Nam, KS Koo, JG
Citation: Jw. Lee et al., Structural modification of a trench by hydrogen annealing, J KOR PHYS, 37(6), 2000, pp. 1034-1039
Characteristics of P-channel SOI LDMOS transistor with tapered field oxides
Authors: Kim, J Kim, SG Roh, TM Park, HS Koo, JG Kim, DY
Citation: J. Kim et al., Characteristics of P-channel SOI LDMOS transistor with tapered field oxides, ETRI J, 21(3), 1999, pp. 22-28
Suppression of corrosion phenomenon on Al-1 %Cu surface with fluorine treatment
Authors: Kim, SG Baek, KH Kim, J Koo, JG Kim, DY Kim, IS Kwon, KH Kim, CI
Citation: Sg. Kim et al., Suppression of corrosion phenomenon on Al-1 %Cu surface with fluorine treatment, J KOR PHYS, 35, 1999, pp. S357-S360
Analysis of etched silicon surfaces for trench isolation techniques
Authors: Kim, SG Kim, J Lee, JW Roh, TM Koo, JG Nam, KS
Citation: Sg. Kim et al., Analysis of etched silicon surfaces for trench isolation techniques, J KOR PHYS, 35, 1999, pp. S374-S378
Characteristics of ultrathin oxide grown by high pressure oxidation for ULSI device applications
Authors: Roh, TM Lee, DW Kim, J Kim, SG Koo, JG Nam, KS Kim, DY
Citation: Tm. Roh et al., Characteristics of ultrathin oxide grown by high pressure oxidation for ULSI device applications, J KOR PHYS, 34, 1999, pp. S538-S541
Effects of drain structures on the hot-carrier degradation of high-voltageLDMOS transistors
Authors: Lee, DW Roh, TM Kim, J Koo, JG Nam, KS Kim, DY Park, HS
Citation: Dw. Lee et al., Effects of drain structures on the hot-carrier degradation of high-voltageLDMOS transistors, J KOR PHYS, 34, 1999, pp. S542-S545
Characteristics of dynamic resistance in a heavily doped silicon semiconductor resistor
Authors: Kim, J Kim, SG Koo, JG Roh, TM Park, HS Kim, DY
Citation: J. Kim et al., Characteristics of dynamic resistance in a heavily doped silicon semiconductor resistor, INT J ELECT, 86(3), 1999, pp. 269-279
Improvement on P-channel SOI LDMOS transistor by adapting a new tapered oxide technique
Authors: Kim, J Kim, SG Song, QS Lee, SY Koo, JG Ma, DS
Citation: J. Kim et al., Improvement on P-channel SOI LDMOS transistor by adapting a new tapered oxide technique, IEEE DEVICE, 46(9), 1999, pp. 1890-1894
Fabrication technology of polysilicon resistors using novel mixed process for analogue CMOS applications
Authors: Lee, DW Roh, TM Park, HS Kim, J Koo, JG Kim, DY
Citation: Dw. Lee et al., Fabrication technology of polysilicon resistors using novel mixed process for analogue CMOS applications, ELECTR LETT, 35(7), 1999, pp. 603-604
Very high density trench gate power MOSFET using simplified four-mask process
Authors: Nam, KS Lee, JW Kim, SG Roh, TM Koo, JG Cho, KI
Citation: Ks. Nam et al., Very high density trench gate power MOSFET using simplified four-mask process, ELECTR LETT, 35(24), 1999, pp. 2149-2150
Integration of high voltage LDMOSFET into a low voltage CMOS for PDP data driver IC
Authors: Roh, TM Lee, DW Song, QS Kim, J Kang, JY Koo, JG Nam, KS
Citation: Tm. Roh et al., Integration of high voltage LDMOSFET into a low voltage CMOS for PDP data driver IC, J KOR PHYS, 33, 1998, pp. S235-S238
Risultati: 1-17 |