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Results: 1-25 | 26-42
Results: 1-25/42
New trap-assisted band-to-band tunneling induced gate current model for p-channel metal-oxide-semiconductor field effect transistors with sub-3 nm oxides
Authors: Lee, HM Liu, CJ Hsu, CW Liang, MS King, YC Hsu, CCH
Citation: Hm. Lee et al., New trap-assisted band-to-band tunneling induced gate current model for p-channel metal-oxide-semiconductor field effect transistors with sub-3 nm oxides, JPN J A P 1, 40(3A), 2001, pp. 1218-1221
Thermally-enhanced remote plasma nitrided ultrathin (1.65 nm) gate oxide with excellent performances in reduction of leakage current and boron diffusion
Authors: Chen, CH Fang, YK Yang, CW Ting, SF Tsair, YS Yu, MC Hou, TH Wang, MF Chen, SC Yu, CH Liang, MS
Citation: Ch. Chen et al., Thermally-enhanced remote plasma nitrided ultrathin (1.65 nm) gate oxide with excellent performances in reduction of leakage current and boron diffusion, IEEE ELEC D, 22(8), 2001, pp. 378-380
The effect of remote plasma nitridation on the integrity of the ultrathin gate dielectric films in 0.13 mu m CMOS technology and beyond
Authors: Ting, SF Fang, YK Chen, CH Yang, CW Hsieh, WT Ho, JJ Yu, MC Jang, SM Yu, CH Liang, MS Chen, S Shih, R
Citation: Sf. Ting et al., The effect of remote plasma nitridation on the integrity of the ultrathin gate dielectric films in 0.13 mu m CMOS technology and beyond, IEEE ELEC D, 22(7), 2001, pp. 327-329
High-quality ultrathin (1.6 nm) nitride/oxide stack gate dielectrics prepared by combining remote plasma nitridation and LPCVD technologies
Authors: Chen, CH Fang, YK Yang, CW Ting, SF Tsair, YS Wang, MF Lin, YM Yu, MC Chen, SC Yu, CH Liang, MS
Citation: Ch. Chen et al., High-quality ultrathin (1.6 nm) nitride/oxide stack gate dielectrics prepared by combining remote plasma nitridation and LPCVD technologies, IEEE ELEC D, 22(6), 2001, pp. 260-262
Leakage mechanism in Cu damascene structure with methylsilane-doped low-K CVD oxide as intermetal dielectric
Authors: Wu, ZC Chiang, CC Wu, WH Chen, MC Jeng, SM Li, LJ Jang, SM Yu, CH Liang, MS
Citation: Zc. Wu et al., Leakage mechanism in Cu damascene structure with methylsilane-doped low-K CVD oxide as intermetal dielectric, IEEE ELEC D, 22(6), 2001, pp. 263-265
Nonsilicide source/drain pixel for 0.25-mu m CMOS image sensor
Authors: Yaung, DN Wuu, SG Fang, YK Wang, CS Tseng, CH Liang, MS
Citation: Dn. Yaung et al., Nonsilicide source/drain pixel for 0.25-mu m CMOS image sensor, IEEE ELEC D, 22(2), 2001, pp. 71-73
To suppress photoexcited current of hydrogenated polysilicon TFTs with lowtemperature oxidation of polychannel
Authors: Yaung, DN Fang, YK Chen, CH Hung, CC Tsao, FC Wuu, SG Liang, MS
Citation: Dn. Yaung et al., To suppress photoexcited current of hydrogenated polysilicon TFTs with lowtemperature oxidation of polychannel, IEEE ELEC D, 22(1), 2001, pp. 23-25
A flash-based SOC technology using a split-gate cell
Authors: Kuo, DS Wang, C Chu, S Liang, MS Tsai, CS Tao, HJ Huang, YC Wu, JR Chen, YT Chih, YD Hsieh, CH Sung, HC Yeh, JK Lin, CJ Wong, SC Lin, SH Hsieh, CT Chu, WT Chen, HP Hsu, C Shyu, DS Peng, SP Fong, TJ Lee, KY
Citation: Ds. Kuo et al., A flash-based SOC technology using a split-gate cell, MICROEL ENG, 59(1-4), 2001, pp. 203-211
Subthreshold characteristics of submicrometer polysilicon thin film transistor
Authors: Yaung, DN Fang, YK Huang, KC Wang, YJ Hung, CC Liang, MS Wuu, SG
Citation: Dn. Yaung et al., Subthreshold characteristics of submicrometer polysilicon thin film transistor, THIN SOL FI, 382(1-2), 2001, pp. 271-274
Effects of post-deposition treatments on ultrathin nitride/oxide gate stack prepared by RTCVD for ULSI devices
Authors: Chen, CH Fang, YK Yang, CW Ting, SF Tsair, YS Wang, MF Chen, SC Yu, CH Liang, MS
Citation: Ch. Chen et al., Effects of post-deposition treatments on ultrathin nitride/oxide gate stack prepared by RTCVD for ULSI devices, SOL ST ELEC, 45(3), 2001, pp. 461-465
A novel programming technique for highly scalable and disturbance immune flash EEPROM
Authors: Huang, KC Fang, YK Yaung, DN Chen, CH Hsu, YL Ting, SF Lin, Y Kuo, DS Wang, CS Liang, MS
Citation: Kc. Huang et al., A novel programming technique for highly scalable and disturbance immune flash EEPROM, SOL ST ELEC, 45(2), 2001, pp. 297-301
Characterization and modeling of edge direct tunneling (EDT) leakage in ultrathin gate oxide MOSFETs
Authors: Yang, KN Huang, HT Chen, MJ Lin, YM Yu, MC Jang, SM Yu, DCH Liang, MS
Citation: Kn. Yang et al., Characterization and modeling of edge direct tunneling (EDT) leakage in ultrathin gate oxide MOSFETs, IEEE DEVICE, 48(6), 2001, pp. 1159-1164
A trap generation closed-form statistical model for intrinsic oxide breakdown
Authors: Huang, HT Chen, MJ Su, CW Chen, JH Hou, CS Liang, MS
Citation: Ht. Huang et al., A trap generation closed-form statistical model for intrinsic oxide breakdown, IEEE DEVICE, 48(6), 2001, pp. 1275-1277
Characterization of hot-hole injection induced SILC and related disturbs in flash memories
Authors: Yih, CM Ho, ZH Liang, MS Chung, SS
Citation: Cm. Yih et al., Characterization of hot-hole injection induced SILC and related disturbs in flash memories, IEEE DEVICE, 48(2), 2001, pp. 300-306
Origins and effects of radical-induced re-oxidation in ultra-thin remote plasma nitrided oxides
Authors: Chen, CH Fang, YK Hsieh, WT Ting, SF Yu, MC Wang, MF Chen, CL Yao, LG Chen, SC Yu, CH Liang, MS
Citation: Ch. Chen et al., Origins and effects of radical-induced re-oxidation in ultra-thin remote plasma nitrided oxides, ELECTR LETT, 37(22), 2001, pp. 1367-1369
He plus remote plasma nitridation of ultra-thin gate oxide for deep submicron CMOS technology applications
Authors: Ting, SF Fang, YK Chen, CH Yang, CW Yu, MC Jang, SM Yu, CH Liang, MS Chen, SW Shih, R
Citation: Sf. Ting et al., He plus remote plasma nitridation of ultra-thin gate oxide for deep submicron CMOS technology applications, ELECTR LETT, 37(12), 2001, pp. 788-790
Dielectric and barrier properties of spin-on organic aromatic low dielectric constant polymers FLARE and SiLK
Authors: Wu, ZC Shiung, ZW Wu, RG Liu, YL Wu, WH Tsui, BY Chen, MC Chang, W Chou, PF Jang, SM Hu, CH Liang, MS
Citation: Zc. Wu et al., Dielectric and barrier properties of spin-on organic aromatic low dielectric constant polymers FLARE and SiLK, J ELCHEM SO, 148(6), 2001, pp. F109-F114
Physical and electrical characteristics of F- and C-doped low dielectric constant chemical vapor deposited oxides
Authors: Wu, ZC Shiung, ZW Chiang, CC Wu, WH Chen, MC Jeng, SM Chang, W Chou, PF Jang, SM Yu, CH Liang, MS
Citation: Zc. Wu et al., Physical and electrical characteristics of F- and C-doped low dielectric constant chemical vapor deposited oxides, J ELCHEM SO, 148(6), 2001, pp. F115-F119
Physical and electrical characteristics of methylsilane- and trimethylsilane-doped low dielectric constant chemical vapor deposited oxides
Authors: Wu, ZC Shiung, ZW Chiang, CC Wu, WH Chen, MC Jeng, SM Chang, W Chou, PF Jang, SM Yu, CH Liang, MS
Citation: Zc. Wu et al., Physical and electrical characteristics of methylsilane- and trimethylsilane-doped low dielectric constant chemical vapor deposited oxides, J ELCHEM SO, 148(6), 2001, pp. F127-F132
Plasma-process-induced damage in sputtered TiN metal-gate capacitors with ultrathin nitrided oxides
Authors: Chen, CC Lin, HC Chang, CY Chao, TS Huang, TY Liang, MS
Citation: Cc. Chen et al., Plasma-process-induced damage in sputtered TiN metal-gate capacitors with ultrathin nitrided oxides, JPN J A P 1, 39(8), 2000, pp. 4733-4737
A comparison of behaviors between hydrogenated/unhydrogenated polysilicon thin film transistors under electric stress
Authors: Yaung, DN Fang, YK Lee, KY Hwang, KC Wuu, SG Liang, MS
Citation: Dn. Yaung et al., A comparison of behaviors between hydrogenated/unhydrogenated polysilicon thin film transistors under electric stress, JPN J A P 1, 39(7A), 2000, pp. 3896-3901
Monte Carlo sphere model for effective oxide thinning induced extrinsic breakdown
Authors: Huang, HT Chen, MJ Chen, JH Su, CW Hou, CS Liang, MS
Citation: Ht. Huang et al., Monte Carlo sphere model for effective oxide thinning induced extrinsic breakdown, JPN J A P 1, 39(4B), 2000, pp. 2026-2029
Improved ultrathin gate oxide integrity in p(+)-polysilicon-gate p-channelmetal oxide semiconductor with medium-dose fluorine implantation
Authors: Chen, CC Lin, HC Chang, CY Huang, TY Chien, CH Liang, MS
Citation: Cc. Chen et al., Improved ultrathin gate oxide integrity in p(+)-polysilicon-gate p-channelmetal oxide semiconductor with medium-dose fluorine implantation, EL SOLID ST, 3(6), 2000, pp. 290-292
Effects of polysilicon gate doping concentration on plasma charging damagein ultrathin gate oxides
Authors: Chen, CC Lin, HC Chang, CY Huang, TY Chien, CH Liang, MS
Citation: Cc. Chen et al., Effects of polysilicon gate doping concentration on plasma charging damagein ultrathin gate oxides, EL SOLID ST, 3(2), 2000, pp. 103-105
The impacts of control gate voltage on the cycling endurance of split gateflash memory
Authors: Huang, KC Fang, YK Yaung, DN Chen, CW Sung, HC Kuo, DS Wang, CS Liang, MS
Citation: Kc. Huang et al., The impacts of control gate voltage on the cycling endurance of split gateflash memory, IEEE ELEC D, 21(7), 2000, pp. 359-361
Risultati: 1-25 | 26-42