ACNP - Italian Periodicals Catalogue

Citation: R. Pendurkar et al., Switching activity generation with automated BIST synthesis for performance testing of interconnects, IEEE COMP A, 20(9), 2001, pp. 1143-1158

Testing of scan circuits containing nonisolated random-logic legacy cores

Authors: Pomeranz, I Zorian, Y

Citation: I. Pomeranz et Y. Zorian, Testing of scan circuits containing nonisolated random-logic legacy cores, IEEE COMP A, 20(8), 2001, pp. 980-993

Boundary scan-based relay wave propagation test of arrays of identical structures

Authors: Sasidhar, K Chatterjee, A Zorian, Y

Citation: K. Sasidhar et al., Boundary scan-based relay wave propagation test of arrays of identical structures, IEEE COMPUT, 50(10), 2001, pp. 1007-1019

Testing the local interconnect resources of SRAM-Based FPGA's

Authors: Renovell, M Portal, JM Figueras, J Zorian, Y

Citation: M. Renovell et al., Testing the local interconnect resources of SRAM-Based FPGA's, J ELEC TEST, 16(5), 2000, pp. 513-520

A high-level EDA environment for the automatic insertion of HD-BIST structures

Authors: Benso, A Cataldo, S Chiusano, S Prinetto, P Zorian, Y

Citation: A. Benso et al., A high-level EDA environment for the automatic insertion of HD-BIST structures, J ELEC TEST, 16(3), 2000, pp. 179-184

An approach to minimize the test configuration for the logic cells of the Xilinx XC4000 FPGAs family

Authors: Renovell, M Portal, JM Figueras, J Zorian, Y

Citation: M. Renovell et al., An approach to minimize the test configuration for the logic cells of the Xilinx XC4000 FPGAs family, J ELEC TEST, 16(3), 2000, pp. 289-299

D&T elevated to bimonthly

Authors: Zorian, Y

Citation: Y. Zorian, D&T elevated to bimonthly, IEEE DES T, 17(4), 2000, pp. 3-3

Power-/energy-efficient BIST schemes for processor data paths

Authors: Kranitis, N Gizopoulos, D Paschalis, A Psarakis, M Zorian, Y

Citation: N. Kranitis et al., Power-/energy-efficient BIST schemes for processor data paths, IEEE DES T, 17(4), 2000, pp. 15-28

Embedded in this issue

Authors: Zorian, Y

Citation: Y. Zorian, Embedded in this issue, IEEE DES T, 17(2), 2000, pp. 5-6

Flexibility and programmability

Authors: Zorian, Y

Citation: Y. Zorian, Flexibility and programmability, IEEE DES T, 17(1), 2000, pp. 3-3

Sequential fault modeling and test pattern generation for CMOS iterative logic arrays

Authors: Psarakis, M Gizopoulos, D Paschalis, A Zorian, Y

Citation: M. Psarakis et al., Sequential fault modeling and test pattern generation for CMOS iterative logic arrays, IEEE COMPUT, 49(10), 2000, pp. 1083-1099

SRAM-based FPGAs: Testing the embedded RAM modules

Authors: Renovell, M Portal, JM Figueras, J Zorian, Y

Citation: M. Renovell et al., SRAM-based FPGAs: Testing the embedded RAM modules, J ELEC TEST, 14(1-2), 1999, pp. 159-167

Integration continues

Authors: Zorian, Y

Citation: Y. Zorian, Integration continues, IEEE DES T, 16(4), 1999, pp. 1-1

Variety at its best

Authors: Zorian, Y

Citation: Y. Zorian, Variety at its best, IEEE DES T, 16(2), 1999, pp. 1-1

Built-in self-test

Authors: Zorian, Y

Citation: Y. Zorian, Built-in self-test, MICROEL ENG, 49(1-2), 1999, pp. 135-138

Challenges in testing core-based system ICs

Authors: Marinissen, EJ Zorian, Y

Citation: Ej. Marinissen et Y. Zorian, Challenges in testing core-based system ICs, IEEE COMM M, 37(6), 1999, pp. 104-109

An effective built-in self-test scheme for parallel multipliers

Authors: Gizopoulos, D Paschalis, A Zorian, Y

Citation: D. Gizopoulos et al., An effective built-in self-test scheme for parallel multipliers, IEEE COMPUT, 48(9), 1999, pp. 936-950

Risultati: 1-25 | 26-27