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Results: 1-25/50
Authors:
ADAMIDES ED
ILIADES P
ARGYRAKIS I
TSALIDES P
THANAILAKIS A
Citation: Ed. Adamides et al., CELLULAR LOGIC BUS ARBITRATION, IEE proceedings. Part E. Computers and digital techniques, 140(6), 1993, pp. 289-296
Authors:
TSAI CT
SUN YN
CHUNG PC
Citation: Ct. Tsai et al., MINIMIZING THE ENERGY OF ACTIVE CONTOUR MODEL USING A HOPFIELD NETWORK, IEE proceedings. Part E. Computers and digital techniques, 140(6), 1993, pp. 297-303
Authors:
RAMANATHAN P
SALUJA KK
FRANKLIN M
Citation: P. Ramanathan et al., TESTING CHECK BITS AT NO COST IN RAMS WITH ON-CHIP ECC, IEE proceedings. Part E. Computers and digital techniques, 140(6), 1993, pp. 304-312
Authors:
PEARCE M
Citation: M. Pearce, MULTILEVEL LOGIC SYNTHESIS FOR PAL DEVICES, IEE proceedings. Part E. Computers and digital techniques, 140(6), 1993, pp. 313-319
Authors:
VAIDYA NH
SINGH AD
KRISHNA CM
Citation: Nh. Vaidya et al., TRADE-OFFS IN DEVELOPING FAULT-TOLERANT SOFTWARE, IEE proceedings. Part E. Computers and digital techniques, 140(6), 1993, pp. 320-326
Authors:
SHIEH MD
WEY CL
FISHER PD
Citation: Md. Shieh et al., FAULT EFFECTS IN ASYNCHRONOUS SEQUENTIAL LOGIC-CIRCUITS, IEE proceedings. Part E. Computers and digital techniques, 140(6), 1993, pp. 327-332
Authors:
DETRY RJ
JAYASUMANA AP
Citation: Rj. Detry et Ap. Jayasumana, 3-LAYER ROUTER FOR CHANNELS WITH CONSTRAINED TERMINALS, IEE proceedings. Part E. Computers and digital techniques, 140(6), 1993, pp. 333-340
Authors:
TAHIR JM
DLAY SS
GORGUINAGUIB RN
HINTON OR
Citation: Jm. Tahir et al., STRONGLY FAULT-SECURE DESIGNS FOR ARITHMETIC-ARRAYS, IEE proceedings. Part E. Computers and digital techniques, 140(6), 1993, pp. 341-347
Authors:
SAUL J
ESCHERMANN B
FROESSL J
Citation: J. Saul et al., 2-LEVEL LOGIC-CIRCUITS USING EXOR SUMS OF PRODUCTS, IEE proceedings. Part E. Computers and digital techniques, 140(6), 1993, pp. 348-356
Authors:
WU H
ZHUANG N
PERKOWSKI MA
Citation: H. Wu et al., SYNTHESIS FOR REED-MULLER DIRECTED ACYCLIC GRAPH NETWORK, IEE proceedings. Part E. Computers and digital techniques, 140(6), 1993, pp. 357-360
Authors:
CHAUDHURI BB
SARKAR N
KUNDU P
Citation: Bb. Chaudhuri et al., IMPROVED FRACTAL GEOMETRY BASED TEXTURE SEGMENTATION TECHNIQUE, IEE proceedings. Part E. Computers and digital techniques, 140(5), 1993, pp. 233-241
Authors:
BARNARD AD
SILVESTER JR
CHAMBERS WG
Citation: Ad. Barnard et al., GUARANTEEING THE PERIOD OF LINEAR RECURRING SEQUENCES (MOD(2E)), IEE proceedings. Part E. Computers and digital techniques, 140(5), 1993, pp. 243-245
Authors:
FITZPATRICK P
MURPHY CC
Citation: P. Fitzpatrick et Cc. Murphy, SOLUTION OF LINEAR-SYSTEMS OF EQUATIONS IN THE PRESENCE OF 2 TRANSIENT HARDWARE FAULTS, IEE proceedings. Part E. Computers and digital techniques, 140(5), 1993, pp. 247-254
Authors:
CHANDRASEKHARAM R
SUBHRAMANIAN S
CHAUDHURY S
Citation: R. Chandrasekharam et al., GENETIC ALGORITHM FOR NODE PARTITIONING PROBLEM AND APPLICATIONS IN VLSI DESIGN, IEE proceedings. Part E. Computers and digital techniques, 140(5), 1993, pp. 255-260
Authors:
JESSHOPE CR
NEDELCHEV IM
HUANG CG
Citation: Cr. Jesshope et al., COMPILATION OF PROCESS ALGEBRA EXPRESSIONS INTO DELAY-INSENSITIVE CIRCUITS, IEE proceedings. Part E. Computers and digital techniques, 140(5), 1993, pp. 261-268
Authors:
HUANG CG
JESSHOPE CR
NEDELCHEV IM
Citation: Cg. Huang et al., SYSTEMATIC METHOD FOR SYNTHESIZING PURELY DELAY-INSENSITIVE CIRCUITS, IEE proceedings. Part E. Computers and digital techniques, 140(5), 1993, pp. 269-276
Authors:
MURTAGH P
TSOI AC
BERGMANN N
Citation: P. Murtagh et al., BIT-SERIAL SYSTOLIC ARRAY IMPLEMENTATION OF A MULTILAYER PERCEPTRON, IEE proceedings. Part E. Computers and digital techniques, 140(5), 1993, pp. 277-288
Authors:
IBRAHIM MK
Citation: Mk. Ibrahim, RADIX-2(N) MULTIPLIER STRUCTURES - A STRUCTURED DESIGN METHODOLOGY, IEE proceedings. Part E. Computers and digital techniques, 140(4), 1993, pp. 185-190
Authors:
BHATTACHARYA S
CHOI YH
TSAI WT
Citation: S. Bhattacharya et al., UNIDIRECTIONAL CUBE-CONNECTED CYCLES, IEE proceedings. Part E. Computers and digital techniques, 140(4), 1993, pp. 191-195
Authors:
WANG CJ
EMNETT F
Citation: Cj. Wang et F. Emnett, AREA AND PERFORMANCE COMPARISON OF PIPELINED RISC PROCESSORS IMPLEMENTING DIFFERENT PRECISE INTERRUPT METHODS, IEE proceedings. Part E. Computers and digital techniques, 140(4), 1993, pp. 196-200
Authors:
HEAL BW
PAGE RMR
Citation: Bw. Heal et Rmr. Page, SIMD MATRIX-METHODS FOR DETECTING HAZARDS IN LOGIC-CIRCUITS, IEE proceedings. Part E. Computers and digital techniques, 140(4), 1993, pp. 201-204
Authors:
STOURAITIS T
CHEN C
Citation: T. Stouraitis et C. Chen, HYBRID SIGNED-DIGIT LOGARITHMIC NUMBER SYSTEM PROCESSOR, IEE proceedings. Part E. Computers and digital techniques, 140(4), 1993, pp. 205-210
Authors:
WANG JJH
CHANG M
FENG WS
Citation: Jjh. Wang et al., BINARY-TREE TIMING SIMULATION WITH CONSIDERATION OF INTERNAL CHARGES, IEE proceedings. Part E. Computers and digital techniques, 140(4), 1993, pp. 211-219
Authors:
MENON SM
JAYASUMANA AP
MALAIYA YK
CLINKINBEARD DR
Citation: Sm. Menon et al., MODELING AND ANALYSIS OF BRIDGING FAULTS IN EMITTER-COUPLED LOGIC (ECL) CIRCUITS, IEE proceedings. Part E. Computers and digital techniques, 140(4), 1993, pp. 220-226
Authors:
AHMAD I
CHEN CYR
Citation: I. Ahmad et Cyr. Chen, DATAPATH SYNTHESIS USING ONCHIP MULTIPORT MEMORIES, IEE proceedings. Part E. Computers and digital techniques, 140(4), 1993, pp. 227-232