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Results:
1-16
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Results: 16
Authors:
Rauly, E
Iniguez, B
Flandre, D
Citation: E. Rauly et al., Investigation of deep submicron single and double gate SOI MOSFETs in accumulation mode for enhanced performance, EL SOLID ST, 4(3), 2001, pp. G28-G30
Authors:
Demeus, L
Dessard, V
Viviani, A
Andriaensen, S
Flandre, D
Citation: L. Demeus et al., Integrated sensor and electronic circuits in fully depleted SOI technologyfor high-temperature applications, IEEE IND E, 48(2), 2001, pp. 272-280
Authors:
Flandre, D
Adriaensen, S
Akheyar, A
Crahay, A
Demeus, L
Delatte, P
Dessard, V
Iniguez, B
Neve, A
Katschmarskyj, B
Loumaye, P
Laconte, J
Martinez, I
Picun, G
Rauly, E
Renaux, C
Spote, D
Zitout, M
Dehan, M
Parvais, B
Simon, P
Vanhoenacker, D
Raskin, JP
Citation: D. Flandre et al., Fully depleted SOICMOS technology for heterogeneous micropower, high-temperature or RF microsystems, SOL ST ELEC, 45(4), 2001, pp. 541-549
Authors:
Vandooren, A
Cristoloveanu, S
Flandre, D
Colinge, JP
Citation: A. Vandooren et al., Hall effect measurements in double-gate SOI MOSFETs, SOL ST ELEC, 45(10), 2001, pp. 1793-1798
Authors:
Vandooren, A
Yuan, J
Flandre, D
Colinge, JP
Citation: A. Vandooren et al., Total-dose effects in double-gate-controlled NPN bipolar transistors, IEEE NUCL S, 48(5), 2001, pp. 1694-1699
Authors:
Iniguez, B
Raskin, JP
Demeus, L
Neve, A
Vanhoenacker, D
Simon, P
Goffioul, M
Flandre, D
Citation: B. Iniguez et al., Deep-submicrometer DC-to-RF SOI MOSFET macro-model, IEEE DEVICE, 48(9), 2001, pp. 1981-1988
Authors:
Pavanello, MA
Martino, JA
Dessard, V
Flandre, D
Citation: Ma. Pavanello et al., An asymmetric channel SOI nMOSFET for reducing parasitic effects and improving output characteristics, EL SOLID ST, 3(1), 2000, pp. 50-52
Authors:
Flandre, D
Citation: D. Flandre, Process alternative: SOI for heterogeneous systems, MICROEL ENG, 54(1-2), 2000, pp. 49-62
Authors:
Pavanello, MA
Martino, JA
Dessard, V
Flandre, D
Citation: Ma. Pavanello et al., Analog performance and application of graded-channel fully depleted SOI MOSFETs, SOL ST ELEC, 44(7), 2000, pp. 1219-1222
Authors:
Pavanello, MA
Martino, JA
Flandre, D
Citation: Ma. Pavanello et al., Graded-channel fully depleted Silicon-On-Insulator nMOSFET for reducing the parasitic bipolar effects, SOL ST ELEC, 44(6), 2000, pp. 917-922
Authors:
Renaux, C
Scheuren, V
Flandre, D
Citation: C. Renaux et al., New experiments on the electrodeposition of iron in porous silicon, MICROEL REL, 40(4-5), 2000, pp. 877-879
Authors:
Flandre, D
Colinge, JP
Chen, J
De Ceuster, D
Eggermont, JP
Ferreira, L
Gentinne, B
Jespers, PGA
Viviani, A
Gillon, R
Raskin, JP
Vander Vorst, A
Vanhoenacker-Janvier, D
Silveira, F
Citation: D. Flandre et al., Fully-depleted SOICMOS technology for low-voltage low-power mixed digital/analog/microwave circuits, ANALOG IN C, 21(3), 1999, pp. 213-228
Authors:
Ernst, T
Vandooren, A
Cristoloveanu, S
Colinge, JP
Flandre, D
Citation: T. Ernst et al., Carrier lifetime extraction in fully depleted dual-gate SOI devices, IEEE ELEC D, 20(5), 1999, pp. 209-211
Authors:
Vandooren, A
Colinge, JP
Flandre, D
Citation: A. Vandooren et al., Gate-all-around OTA's for rad-hard and high-temperature analog applications, IEEE NUCL S, 46(4), 1999, pp. 1242-1249
Authors:
Iniguez, B
Gentinne, B
Dessard, V
Flandre, D
Citation: B. Iniguez et al., A physically-based C-infinity-continuous model for accumulation-mode SOI pMOSFET's, IEEE DEVICE, 46(12), 1999, pp. 2295-2303
Authors:
Viviani, A
Flandre, D
Jespers, P
Citation: A. Viviani et al., High-temperature sigma-delta modulator in thin-film fully-depleted SOI technology, ELECTR LETT, 35(9), 1999, pp. 749-751
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