AAAAAA

   
Results: 1-18 |
Results: 18
MOS-TRANSISTORS WITH STACKED SIO2-TA2O5-SIO2 GATE DIELECTRICS FOR GIGA-SCALE INTEGRATION OF CMOS TECHNOLOGIES
Authors: KIZILYALLI IC HUANG RYS ROY PK
Citation: Ic. Kizilyalli et al., MOS-TRANSISTORS WITH STACKED SIO2-TA2O5-SIO2 GATE DIELECTRICS FOR GIGA-SCALE INTEGRATION OF CMOS TECHNOLOGIES, IEEE electron device letters, 19(11), 1998, pp. 423-425
IMPROVEMENT OF HOT-CARRIER RELIABILITY WITH DEUTERIUM ANNEALS FOR MANUFACTURING MULTILEVEL METAL DIELECTRIC MOS SYSTEMS/
Authors: KIZILYALLI IC ABELN GC CHEN Z LEE J WEBER G KOTZIAS B CHETLUR S LYDING JW HESS K
Citation: Ic. Kizilyalli et al., IMPROVEMENT OF HOT-CARRIER RELIABILITY WITH DEUTERIUM ANNEALS FOR MANUFACTURING MULTILEVEL METAL DIELECTRIC MOS SYSTEMS/, IEEE electron device letters, 19(11), 1998, pp. 444-446
ULTRAHIGH VACUUM-SCANNING TUNNELING MICROSCOPY NANOFABRICATION AND HYDROGEN DEUTERIUM DESORPTION FROM SILICON SURFACES - IMPLICATIONS FOR COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR TECHNOLOGY/
Authors: LYDING JW HESS K ABELN GC THOMPSON DS MOORE JS HERSAM MC FOLEY ET LEE J CHEN Z HWANG ST CHOI H AVOURIS P KIZILYALLI IC
Citation: Jw. Lyding et al., ULTRAHIGH VACUUM-SCANNING TUNNELING MICROSCOPY NANOFABRICATION AND HYDROGEN DEUTERIUM DESORPTION FROM SILICON SURFACES - IMPLICATIONS FOR COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR TECHNOLOGY/, Applied surface science, 132, 1998, pp. 221-230
COUPLED ELECTRON-HOLE DYNAMICS AT THE SI SIO2 INTERFACE/
Authors: WANG W LUPKE G DIVENTRA M PANTELIDES ST GILLIGAN JM TOLK NH KIZILYALLI IC ROY PK MARGARITONDO G LUCOVSKY G
Citation: W. Wang et al., COUPLED ELECTRON-HOLE DYNAMICS AT THE SI SIO2 INTERFACE/, Physical review letters, 81(19), 1998, pp. 4224-4227
GIANT ISOTOPE EFFECT IN HOT-ELECTRON DEGRADATION OF METAL-OXIDE-SILICON DEVICES
Authors: HESS K KIZILYALLI IC LYDING JW
Citation: K. Hess et al., GIANT ISOTOPE EFFECT IN HOT-ELECTRON DEGRADATION OF METAL-OXIDE-SILICON DEVICES, I.E.E.E. transactions on electron devices, 45(2), 1998, pp. 406-416
STACKED HIGH-EPSILON GATE DIELECTRIC FOR GIGASCALE INTEGRATION OF METAL-OXIDE-SEMICONDUCTOR TECHNOLOGIES
Authors: ROY PK KIZILYALLI IC
Citation: Pk. Roy et Ic. Kizilyalli, STACKED HIGH-EPSILON GATE DIELECTRIC FOR GIGASCALE INTEGRATION OF METAL-OXIDE-SEMICONDUCTOR TECHNOLOGIES, Applied physics letters, 72(22), 1998, pp. 2835-2837
DEUTERIUM POST-METAL ANNEALING OF MOSFETS FOR IMPROVED HOT-CARRIER RELIABILITY
Authors: KIZILYALLI IC LYDING JW HESS K
Citation: Ic. Kizilyalli et al., DEUTERIUM POST-METAL ANNEALING OF MOSFETS FOR IMPROVED HOT-CARRIER RELIABILITY, IEEE electron device letters, 18(3), 1997, pp. 81-83
SILICON NPN BIPOLAR-TRANSISTORS WITH INDIUM-IMPLANTED BASE REGIONS
Authors: KIZILYALLI IC CHEN AS NAGY WJ RICH TL HAM TE LEE KH CARROLL MS IANNUZZI M
Citation: Ic. Kizilyalli et al., SILICON NPN BIPOLAR-TRANSISTORS WITH INDIUM-IMPLANTED BASE REGIONS, IEEE electron device letters, 18(3), 1997, pp. 120-122
N(-POLYSILICON GATE PMOSFETS WITH INDIUM-DOPED BURIED-CHANNELS())
Authors: KIZILYALLI IC STEVIE FA BUDE JD
Citation: Ic. Kizilyalli et al., N(-POLYSILICON GATE PMOSFETS WITH INDIUM-DOPED BURIED-CHANNELS()), IEEE electron device letters, 17(2), 1996, pp. 46-49
DIFFUSION PARAMETERS OF INDIUM FOR SILICON PROCESS MODELING
Authors: KIZILYALLI IC RICH TL STEVIE FA RAFFERTY CS
Citation: Ic. Kizilyalli et al., DIFFUSION PARAMETERS OF INDIUM FOR SILICON PROCESS MODELING, Journal of applied physics, 80(9), 1996, pp. 4944-4947
ACCURATE BASE AND COLLECTOR CURRENT MODELING OF POLYSILICON EMITTER BIPOLAR-TRANSISTORS - QUANTIFICATION OF HOLE SURFACE RECOMBINATION VELOCITY
Authors: KIZILYALLI IC RAMBAUD MM HAM TE STEVIE FA KAHORA PM ZANESKI G THOMA MJ BOULIN DM
Citation: Ic. Kizilyalli et al., ACCURATE BASE AND COLLECTOR CURRENT MODELING OF POLYSILICON EMITTER BIPOLAR-TRANSISTORS - QUANTIFICATION OF HOLE SURFACE RECOMBINATION VELOCITY, Journal of applied physics, 79(5), 1996, pp. 2738-2744
REDUCTION OF HOT-ELECTRON DEGRADATION IN METAL-OXIDE-SEMICONDUCTOR TRANSISTORS BY DEUTERIUM PROCESSING
Authors: LYDING JW HESS K KIZILYALLI IC
Citation: Jw. Lyding et al., REDUCTION OF HOT-ELECTRON DEGRADATION IN METAL-OXIDE-SEMICONDUCTOR TRANSISTORS BY DEUTERIUM PROCESSING, Applied physics letters, 68(18), 1996, pp. 2526-2528
HIGH-PERFORMANCE 3.3- AND 5-V 0.5-MU-M CMOS TECHNOLOGY FOR ASICS
Authors: KIZILYALLI IC THOMA MJ LYTLE SA MARTIN EP SINGH R VITKAVAGE SC BECHTOLD PF KEARNEY JW RAMBAUD MM TWIFORD MS COCHRAN WT FENSTERMAKER LR FREYMAN R SUN WS DUNCAN A
Citation: Ic. Kizilyalli et al., HIGH-PERFORMANCE 3.3- AND 5-V 0.5-MU-M CMOS TECHNOLOGY FOR ASICS, IEEE transactions on semiconductor manufacturing, 8(4), 1995, pp. 440-448
THRESHOLD VOLTAGE MINIMUM GATE LENGTH TRADE-OFF IN BURIED-CHANNEL PMOS DEVICES FOR SCALED SUPPLY VOLTAGE CMOS TECHNOLOGIES
Authors: KIZILYALLI IC RAMBAUD MM DUNCAN A LYTLE SA THOMA MJ
Citation: Ic. Kizilyalli et al., THRESHOLD VOLTAGE MINIMUM GATE LENGTH TRADE-OFF IN BURIED-CHANNEL PMOS DEVICES FOR SCALED SUPPLY VOLTAGE CMOS TECHNOLOGIES, IEEE electron device letters, 16(10), 1995, pp. 457-459
TECHNOLOGY CAD AT AT-AND-T
Authors: LLOYD P MCANDREW CC MCLENNAN MJ NASSIF SR SINGHAL K SINGHAL K ZEITZOFF PM DARWISH MN HARUTA K LENTZ JL VUONG HH PINTO MR RAFFERTY CS KIZILYALLI IC
Citation: P. Lloyd et al., TECHNOLOGY CAD AT AT-AND-T, Microelectronics, 26(2-3), 1995, pp. 79-97
IMPROVED CIRCUIT TECHNIQUE TO REDUCE H(FE) DEGRADATION IN BIPOLAR OUTPUT DRIVERS
Authors: KIZILYALLI IC MCANDREW CC
Citation: Ic. Kizilyalli et Cc. Mcandrew, IMPROVED CIRCUIT TECHNIQUE TO REDUCE H(FE) DEGRADATION IN BIPOLAR OUTPUT DRIVERS, I.E.E.E. transactions on electron devices, 42(3), 1995, pp. 573-574
DEGRADATION OF GAIN IN BIPOLAR-TRANSISTORS
Authors: KIZILYALLI IC BUDE JD
Citation: Ic. Kizilyalli et Jd. Bude, DEGRADATION OF GAIN IN BIPOLAR-TRANSISTORS, I.E.E.E. transactions on electron devices, 41(7), 1994, pp. 1083-1091
PREDICTIVE WORST CASE STATISTICAL MODELING OF 0.8-MU-M BICMOS BIPOLAR-TRANSISTORS - A METHODOLOGY BASED ON PROCESS AND MIXED DEVICE CIRCUITLEVEL SIMULATORS
Authors: KIZILYALLI IC HAM TE SINGHAL K KEARNEY JW LIN W THOMA MJ
Citation: Ic. Kizilyalli et al., PREDICTIVE WORST CASE STATISTICAL MODELING OF 0.8-MU-M BICMOS BIPOLAR-TRANSISTORS - A METHODOLOGY BASED ON PROCESS AND MIXED DEVICE CIRCUITLEVEL SIMULATORS, I.E.E.E. transactions on electron devices, 40(5), 1993, pp. 966-973
Risultati: 1-18 |