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Results: 1-13 |
Results: 13
A MEMS based amperometric detector for E-Coli bacteria using self-assembled monolayers
Authors: Gau, JJ Lan, EH Dunn, B Ho, CM Woo, JCS
Citation: Jj. Gau et al., A MEMS based amperometric detector for E-Coli bacteria using self-assembled monolayers, BIOSENS BIO, 16(9-12), 2001, pp. 745-755
A study of hot-carrier induced interface-trap profiles in lateral asymmetric channel MOSFETs using a novel charge pumping technique
Authors: Mahapatra, S Rao, VR Vasi, J Cheng, B Woo, JCS
Citation: S. Mahapatra et al., A study of hot-carrier induced interface-trap profiles in lateral asymmetric channel MOSFETs using a novel charge pumping technique, SOL ST ELEC, 45(10), 2001, pp. 1717-1723
Comprehensive study on low-frequency noise characteristics in surface channel SOICMOSFETs and device design optimization for RF ICs
Authors: Tseng, YC Huang, WM Mendicino, M Monk, DJ Welch, PJ Woo, JCS
Citation: Yc. Tseng et al., Comprehensive study on low-frequency noise characteristics in surface channel SOICMOSFETs and device design optimization for RF ICs, IEEE DEVICE, 48(7), 2001, pp. 1428-1437
Performance and hot-carrier reliability of 100 nm channel length jet vapordeposited Si3N4 MNSFETs
Authors: Mahapatra, S Rao, VR Cheng, B Khare, M Parikh, CD Woo, JCS Vasi, JM
Citation: S. Mahapatra et al., Performance and hot-carrier reliability of 100 nm channel length jet vapordeposited Si3N4 MNSFETs, IEEE DEVICE, 48(4), 2001, pp. 679-684
Sub-100 nm Gamma-gate MOSFET's with self-aligned drain extension formed bysolid phase diffusion
Authors: To, KH Woo, JCS
Citation: Kh. To et Jcs. Woo, Sub-100 nm Gamma-gate MOSFET's with self-aligned drain extension formed bysolid phase diffusion, IEEE ELEC D, 21(2), 2000, pp. 79-81
AC floating body effects in partially depleted floating body SOI nMOS operated at elevated temperature: An analog circuit prospective
Authors: Tseng, YC Huang, WM Hwang, C Woo, JCS
Citation: Yc. Tseng et al., AC floating body effects in partially depleted floating body SOI nMOS operated at elevated temperature: An analog circuit prospective, IEEE ELEC D, 21(10), 2000, pp. 494-496
Floating body induced pre-kink excess low-frequency noise in submicron SOICMOSFET technology
Authors: Tseng, YC Huang, WM Ilderem, V Woo, JCS
Citation: Yc. Tseng et al., Floating body induced pre-kink excess low-frequency noise in submicron SOICMOSFET technology, IEEE ELEC D, 20(9), 1999, pp. 484-486
Exploration of velocity overshoot in a high-performance deep sub-0.1-mu m SOI MOSFET with asymmetric channel profile
Authors: Cheng, BH Rao, VR Woo, JCS
Citation: Bh. Cheng et al., Exploration of velocity overshoot in a high-performance deep sub-0.1-mu m SOI MOSFET with asymmetric channel profile, IEEE ELEC D, 20(10), 1999, pp. 538-540
Phase noise characteristics associated with low-frequency noise in submicron SOI MOSFET feedback oscillator for RF IC's
Authors: Tseng, YC Huang, WM Spears, E Spooner, D Ngo, D Ford, JM Woo, JCS
Citation: Yc. Tseng et al., Phase noise characteristics associated with low-frequency noise in submicron SOI MOSFET feedback oscillator for RF IC's, IEEE ELEC D, 20(1), 1999, pp. 54-56
A study of 100 nm channel length asymmetric channel MOSFET by using chargepumping
Authors: Mahapatra, S Rao, VR Parikh, CD Vasi, J Cheng, B Woo, JCS
Citation: S. Mahapatra et al., A study of 100 nm channel length asymmetric channel MOSFET by using chargepumping, MICROEL ENG, 48(1-4), 1999, pp. 193-196
AC floating body effects and the resultant analog circuit issues in submicron floating body and body-grounded SOI MOSFET's
Authors: Tseng, YC Huang, WM Monk, DJ Welch, P Ford, JM Woo, JCS
Citation: Yc. Tseng et al., AC floating body effects and the resultant analog circuit issues in submicron floating body and body-grounded SOI MOSFET's, IEEE DEVICE, 46(8), 1999, pp. 1685-1692
The impact of high-kappa gate dielectrics and metal gate electrodes on sub-100 nm MOSFET's
Authors: Cheng, BH Cao, M Rao, R Inani, A Voorde, PV Greene, WM Stork, JMC Yu, ZP Zeitzoff, PM Woo, JCS
Citation: Bh. Cheng et al., The impact of high-kappa gate dielectrics and metal gate electrodes on sub-100 nm MOSFET's, IEEE DEVICE, 46(7), 1999, pp. 1537-1544
Design considerations of high-kappa gate dielectrics for sub-0.1-mu m MOSFET's
Authors: Cheng, BH Cao, M Vande Voorde, P Greene, W Stork, H Yu, ZP Woo, JCS
Citation: Bh. Cheng et al., Design considerations of high-kappa gate dielectrics for sub-0.1-mu m MOSFET's, IEEE DEVICE, 46(1), 1999, pp. 261-262
Risultati: 1-13 |