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Results: 1-16 |
Results: 16
ONLINE FAULT-DETECTION FOR BUS-BASED FIELD-PROGRAMMABLE GATE ARRAYS
Authors: SHNIDMAN NR MANGIONESMITH WH POTKONJAK M
Citation: Nr. Shnidman et al., ONLINE FAULT-DETECTION FOR BUS-BASED FIELD-PROGRAMMABLE GATE ARRAYS, IEEE transactions on very large scale integration (VLSI) systems, 6(4), 1998, pp. 656-666
LOW OVERHEAD FAULT-TOLERANT FPGA SYSTEMS
Authors: LACH J MANGIONESMITH WH POTKONJAK M
Citation: J. Lach et al., LOW OVERHEAD FAULT-TOLERANT FPGA SYSTEMS, IEEE transactions on very large scale integration (VLSI) systems, 6(2), 1998, pp. 212-221
BEHAVIORAL-LEVEL SYNTHESIS OF HETEROGENEOUS BISR RECONFIGURABLE ASICS
Authors: GUERRA LM POTKONJAK M RABAEY JM
Citation: Lm. Guerra et al., BEHAVIORAL-LEVEL SYNTHESIS OF HETEROGENEOUS BISR RECONFIGURABLE ASICS, IEEE transactions on very large scale integration (VLSI) systems, 6(1), 1998, pp. 158-167
A CONTROLLER REDESIGN TECHNIQUE TO ENHANCE TESTABILITY OF CONTROLLER DATA-PATH CIRCUITS
Authors: DEY S GANGARAM V POTKONJAK M
Citation: S. Dey et al., A CONTROLLER REDESIGN TECHNIQUE TO ENHANCE TESTABILITY OF CONTROLLER DATA-PATH CIRCUITS, IEEE transactions on computer-aided design of integrated circuits and systems, 17(2), 1998, pp. 157-168
BEHAVIORAL OPTIMIZATION USING THE MANIPULATION OF TIMING CONSTRAINTS
Authors: POTKONJAK M SRIVASTAVA M
Citation: M. Potkonjak et M. Srivastava, BEHAVIORAL OPTIMIZATION USING THE MANIPULATION OF TIMING CONSTRAINTS, IEEE transactions on computer-aided design of integrated circuits and systems, 17(10), 1998, pp. 936-947
NONSCAN DESIGN-FOR-TESTABILITY TECHNIQUES USING RT-LEVEL DESIGN INFORMATION
Authors: DEY S POTKONJAK M
Citation: S. Dey et M. Potkonjak, NONSCAN DESIGN-FOR-TESTABILITY TECHNIQUES USING RT-LEVEL DESIGN INFORMATION, IEEE transactions on computer-aided design of integrated circuits and systems, 16(12), 1997, pp. 1488-1506
PERFORMANCE OPTIMIZATION USING TEMPLATE MAPPING FOR DATAPATH-INTENSIVE HIGH-LEVEL SYNTHESIS
Authors: CORAZAO MR KHALAF MA GUERRA LM POTKONJAK M RABAEY JM
Citation: Mr. Corazao et al., PERFORMANCE OPTIMIZATION USING TEMPLATE MAPPING FOR DATAPATH-INTENSIVE HIGH-LEVEL SYNTHESIS, IEEE transactions on computer-aided design of integrated circuits and systems, 15(8), 1996, pp. 877-888
MULTIPLE CONSTANT MULTIPLICATIONS - EFFICIENT AND VERSATILE FRAMEWORKAND ALGORITHMS FOR EXPLORING COMMON SUBEXPRESSION ELIMINATION
Authors: POTKONJAK M SRIVASTAVA MB CHANDRAKASAN AP
Citation: M. Potkonjak et al., MULTIPLE CONSTANT MULTIPLICATIONS - EFFICIENT AND VERSATILE FRAMEWORKAND ALGORITHMS FOR EXPLORING COMMON SUBEXPRESSION ELIMINATION, IEEE transactions on computer-aided design of integrated circuits and systems, 15(2), 1996, pp. 151-165
OPTIMUM AND HEURISTIC TRANSFORMATION TECHNIQUES FOR SIMULTANEOUS-OPTIMIZATION OF LATENCY AND THROUGHPUT
Authors: SRIVASTAVA MB POTKONJAK M
Citation: Mb. Srivastava et M. Potkonjak, OPTIMUM AND HEURISTIC TRANSFORMATION TECHNIQUES FOR SIMULTANEOUS-OPTIMIZATION OF LATENCY AND THROUGHPUT, IEEE transactions on very large scale integration (VLSI) systems, 3(1), 1995, pp. 2-19
SYNTHESIS TECHNIQUES FOR LOW-POWER DIGITAL DESIGNS
Authors: POTKONJAK M ASHAR P DEY S MISAWA T ROY RK
Citation: M. Potkonjak et al., SYNTHESIS TECHNIQUES FOR LOW-POWER DIGITAL DESIGNS, NEC research & development, 36(1), 1995, pp. 83-102
BEHAVIORAL SYNTHESIS OF AREA-EFFICIENT TESTABLE DESIGNS USING INTERACTION BETWEEN HARDWARE SHARING AND PARTIAL SCAN
Authors: POTKONJAK M DEY S ROY RK
Citation: M. Potkonjak et al., BEHAVIORAL SYNTHESIS OF AREA-EFFICIENT TESTABLE DESIGNS USING INTERACTION BETWEEN HARDWARE SHARING AND PARTIAL SCAN, IEEE transactions on computer-aided design of integrated circuits and systems, 14(9), 1995, pp. 1141-1154
CONSIDERING TESTABILITY AT BEHAVIORAL LEVEL - USE OF TRANSFORMATIONS FOR PARTIAL SCAN COST MINIMIZATION UNDER TIMING AND AREA CONSTRAINTS
Authors: POTKONJAK M DEY S ROY RK
Citation: M. Potkonjak et al., CONSIDERING TESTABILITY AT BEHAVIORAL LEVEL - USE OF TRANSFORMATIONS FOR PARTIAL SCAN COST MINIMIZATION UNDER TIMING AND AREA CONSTRAINTS, IEEE transactions on computer-aided design of integrated circuits and systems, 14(5), 1995, pp. 531-546
OPTIMIZING POWER USING TRANSFORMATIONS
Authors: CHANDRAKASAN AP POTKONJAK M MEHRA R RABAEY J BRODERSEN RW
Citation: Ap. Chandrakasan et al., OPTIMIZING POWER USING TRANSFORMATIONS, IEEE transactions on computer-aided design of integrated circuits and systems, 14(1), 1995, pp. 12-31
OPTIMIZING THROUGHPUT AND RESOURCE UTILIZATION USING PIPELINING - TRANSFORMATION BASED APPROACH
Authors: POTKONJAK M RABAEY J
Citation: M. Potkonjak et J. Rabaey, OPTIMIZING THROUGHPUT AND RESOURCE UTILIZATION USING PIPELINING - TRANSFORMATION BASED APPROACH, Journal of VLSI signal processing, 8(2), 1994, pp. 117-130
ESTIMATING IMPLEMENTATION BOUNDS FOR REAL-TIME DSP APPLICATION-SPECIFIC CIRCUITS
Authors: RABAEY JM POTKONJAK M
Citation: Jm. Rabaey et M. Potkonjak, ESTIMATING IMPLEMENTATION BOUNDS FOR REAL-TIME DSP APPLICATION-SPECIFIC CIRCUITS, IEEE transactions on computer-aided design of integrated circuits and systems, 13(6), 1994, pp. 669-683
OPTIMIZING RESOURCE UTILIZATION USING TRANSFORMATIONS
Authors: POTKONJAK M RABAEY J
Citation: M. Potkonjak et J. Rabaey, OPTIMIZING RESOURCE UTILIZATION USING TRANSFORMATIONS, IEEE transactions on computer-aided design of integrated circuits and systems, 13(3), 1994, pp. 277-292
Risultati: 1-16 |