Authors:
KOH YH
OH MR
LEE JW
YANG JW
LEE WC
KIM HK
Citation: Yh. Koh et al., BODY-CONTACTED SOI MOSFET STRUCTURE AND ITS APPLICATION TO DRAM, I.E.E.E. transactions on electron devices, 45(5), 1998, pp. 1063-1070
Citation: T. Ohno et al., SUPPRESSION OF PARASITIC BIPOLAR ACTION IN ULTRA-THIN-FILM FULLY-DEPLETED CMOS SIMOX DEVICES BY AR-ION IMPLANTATION INTO SOURCE/DRAIN REGIONS/, I.E.E.E. transactions on electron devices, 45(5), 1998, pp. 1071-1076
Citation: M. Horiuchi et M. Tamura, BESS - A SOURCE STRUCTURE THAT FULLY SUPPRESSES THE FLOATING BODY EFFECTS IN SOI CMOSFETS, I.E.E.E. transactions on electron devices, 45(5), 1998, pp. 1077-1083
Citation: Tc. Hsiao et al., ADVANCED TECHNOLOGIES FOR OPTIMIZED SUB-QUARTER-MICROMETER SOI CMOS DEVICES, I.E.E.E. transactions on electron devices, 45(5), 1998, pp. 1092-1098
Citation: Hi. Liu et al., THIN SILICIDE DEVELOPMENT FOR FULLY-DEPLETED SOI CMOS TECHNOLOGY, I.E.E.E. transactions on electron devices, 45(5), 1998, pp. 1099-1104
Citation: Skh. Fung et al., IMPACT OF SCALING SILICON FILM THICKNESS AND CHANNEL WIDTH ON SOI MOSFET WITH REOXIDIZED MESA ISOLATION, I.E.E.E. transactions on electron devices, 45(5), 1998, pp. 1105-1110
Authors:
HORIUCHI M
TESHIMA T
TOKUMASU K
YAMAGUCHI K
Citation: M. Horiuchi et al., HIGH-CURRENT SMALL-PARASITIC-CAPACITANCE MOSFET ON A POLY-SI INTERLAYERED (PSI-PSI) SOI WAFER, I.E.E.E. transactions on electron devices, 45(5), 1998, pp. 1111-1115
Citation: T. Tsuchiya et al., 3 MECHANISMS DETERMINING SHORT-CHANNEL EFFECTS IN FULLY-DEPLETED SOI MOSFETS, I.E.E.E. transactions on electron devices, 45(5), 1998, pp. 1116-1121
Authors:
GAMIZ F
LOPEZVILLANUEVA JA
ROLDAN JB
CARCELLER JE
CARTUJO P
Citation: F. Gamiz et al., MONTE-CARLO SIMULATION OF ELECTRON-TRANSPORT PROPERTIES IN EXTREMELY THIN SOI MOSFETS, I.E.E.E. transactions on electron devices, 45(5), 1998, pp. 1122-1126
Citation: B. Majkusiak et al., SEMICONDUCTOR THICKNESS EFFECTS IN THE DOUBLE-GATE SOI MOSFET, I.E.E.E. transactions on electron devices, 45(5), 1998, pp. 1127-1134
Authors:
SELMI L
PAVESI M
WONG HSP
ACOVIC A
SANGIORGI E
Citation: L. Selmi et al., MONITORING HOT-CARRIER DEGRADATION IN SOI MOSFETS BY HOT-CARRIER LUMINESCENCE TECHNIQUES, I.E.E.E. transactions on electron devices, 45(5), 1998, pp. 1135-1139
Citation: Sh. Renn et al., HOT-CARRIER EFFECTS AND LIFETIME PREDICTION IN OFF-STATE OPERATION OFDEEP-SUBMICRON SOI N-MOSFETS, I.E.E.E. transactions on electron devices, 45(5), 1998, pp. 1140-1146
Citation: De. Ioannou et al., OPPOSITE-CHANNEL-BASED INJECTION OF HOT-CARRIERS IN SOI MOSFETS - PHYSICS AND APPLICATIONS, I.E.E.E. transactions on electron devices, 45(5), 1998, pp. 1147-1154
Citation: V. Nagapudi et al., EFFECT OF COLLECTOR STRUCTURE ON THE FBSOA OF THE DIELECTRICALLY-ISOLATED LIGBT, I.E.E.E. transactions on electron devices, 45(5), 1998, pp. 1155-1161
Citation: Cw. Wang et al., THE RELATION BETWEEN LUMINOUS PROPERTIES AND OXYGEN-CONTENT IN ZNS-TBOF THIN-FILM ELECTROLUMINESCENT DEVICES FABRICATED BY RADIOFREQUENCY MAGNETRON SPUTTERING METHOD, I.E.E.E. transactions on electron devices, 45(4), 1998, pp. 757-762
Citation: Yk. Su et al., HIGH-PERFORMANCE 670-NM ALGAINP GAINP VISIBLE STRAINED-QUANTUM-WELL LASERS/, I.E.E.E. transactions on electron devices, 45(4), 1998, pp. 763-767
Citation: K. Neyts et D. Corlatan, SIMULATION AND MEASUREMENT OF MULTIPLICATION IN THIN-FILM ELECTROLUMINESCENT DEVICES WITH DOPED PROBE LAYERS, I.E.E.E. transactions on electron devices, 45(4), 1998, pp. 768-777
Authors:
ANDOH F
KOSUGI M
KAWAMURA T
ARAKI S
TAKETOSHI K
Citation: F. Andoh et al., DEVELOPMENT OF A NOVEL IMAGE INTENSIFIER OF AN AMPLIFIED METAL-OXIDE-SEMICONDUCTOR IMAGER OVERLAID WITH ELECTRON-BOMBARDED AMORPHOUS-SILICON, I.E.E.E. transactions on electron devices, 45(4), 1998, pp. 778-784
Citation: Rs. Okojie et al., CHARACTERIZATION OF HIGHLY DOPED N-TYPE AND P-TYPE 6H-SIC PIEZORESISTORS, I.E.E.E. transactions on electron devices, 45(4), 1998, pp. 785-790
Citation: Dc. Herbert, THEORY OF SIGE WAVE-GUIDE AVALANCHE DETECTORS OPERATING AT LAMBDA = 1.3 MU-M, I.E.E.E. transactions on electron devices, 45(4), 1998, pp. 791-796
Citation: Mc. Hu et Sl. Jang, AN ANALYTICAL FULLY-DEPLETED SOI MOSFET MODEL CONSIDERING THE EFFECTSOF SELF-HEATING AND SOURCE DRAIN RESISTANCE/, I.E.E.E. transactions on electron devices, 45(4), 1998, pp. 797-801
Authors:
SELMI L
MASTRAPASQUA M
BOULIN DM
BUDE JD
PAVESI M
SANGIORGI E
PINTO MR
Citation: L. Selmi et al., VERIFICATION OF ELECTRON DISTRIBUTIONS IN SILICON BY MEANS OF HOT-CARRIER LUMINESCENCE MEASUREMENTS, I.E.E.E. transactions on electron devices, 45(4), 1998, pp. 802-808
Authors:
NODA K
TATSUMI T
UCHIDA T
NAKAJIMA K
MIYAMOTO H
HU CM
Citation: K. Noda et al., A 0.1-MU-M DELTA-DOPED MOSFET FABRICATED WITH POST-LOW-ENERGY IMPLANTING SELECTIVE EPITAXY, I.E.E.E. transactions on electron devices, 45(4), 1998, pp. 809-814
Citation: T. Amazawa et al., PLANARIZED MULTILEVEL INTERCONNECTION USING CHEMICAL-MECHANICAL POLISHING OF SELECTIVE CVD-AL VIA PLUGS, I.E.E.E. transactions on electron devices, 45(4), 1998, pp. 815-820