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Results: 1-25 | 26-26
Results: 1-25/26
AUTOMATED SYNTHESIS OF SKEW-BASED CLOCK DISTRIBUTION NETWORKS
Authors: NEVES JL FRIEDMAN EG
Citation: Jl. Neves et Eg. Friedman, AUTOMATED SYNTHESIS OF SKEW-BASED CLOCK DISTRIBUTION NETWORKS, VLSI design, 7(1), 1998, pp. 31-57
REPEATER DESIGN TO REDUCE DELAY AND POWER IN RESISTIVE INTERCONNECT
Authors: ADLER V FRIEDMAN EG
Citation: V. Adler et Eg. Friedman, REPEATER DESIGN TO REDUCE DELAY AND POWER IN RESISTIVE INTERCONNECT, IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 45(5), 1998, pp. 607-616
HIGH-PERFORMANCE CLOCK DISTRIBUTION NETWORKS
Authors: FRIEDMAN EG
Citation: Eg. Friedman, HIGH-PERFORMANCE CLOCK DISTRIBUTION NETWORKS, Journal of VLSI signal processing systems for signal, image, and video technology, 16(2-3), 1997, pp. 113-116
BUFFERED CLOCK TREE SYNTHESIS WITH NONZERO CLOCK SKEW SCHEDULING FOR INCREASED TOLERANCE TO PROCESS PARAMETER VARIATIONS
Authors: NEVES JL FRIEDMAN EG
Citation: Jl. Neves et Eg. Friedman, BUFFERED CLOCK TREE SYNTHESIS WITH NONZERO CLOCK SKEW SCHEDULING FOR INCREASED TOLERANCE TO PROCESS PARAMETER VARIATIONS, Journal of VLSI signal processing systems for signal, image, and video technology, 16(2-3), 1997, pp. 149-161
TIMING OF MULTIGIGAHERTZ RAPID SINGLE FLUX QUANTUM DIGITAL CIRCUITS
Authors: GAJ K FRIEDMAN EG FELDMAN MJ
Citation: K. Gaj et al., TIMING OF MULTIGIGAHERTZ RAPID SINGLE FLUX QUANTUM DIGITAL CIRCUITS, Journal of VLSI signal processing systems for signal, image, and video technology, 16(2-3), 1997, pp. 247-276
A HYBRID RADIX-4 RADIX-8 LOW-POWER SIGNED MULTIPLIER ARCHITECTURE/
Authors: CHERKAUER BS FRIEDMAN EG
Citation: Bs. Cherkauer et Eg. Friedman, A HYBRID RADIX-4 RADIX-8 LOW-POWER SIGNED MULTIPLIER ARCHITECTURE/, IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 44(8), 1997, pp. 656-659
INTRODUCTION TO THE SPECIAL ISSUE ON LOW-POWER WIRELESS COMMUNICATIONS
Authors: KIAEI S FRIEDMAN EG
Citation: S. Kiaei et Eg. Friedman, INTRODUCTION TO THE SPECIAL ISSUE ON LOW-POWER WIRELESS COMMUNICATIONS, IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 44(6), 1997, pp. 425-427
A COMPARISON OF ANALOG AND DIGITAL CIRCUIT IMPLEMENTATIONS OF LOW-POWER MATCHED-FILTERS FOR USE IN PORTABLE WIRELESS COMMUNICATION TERMINALS
Authors: HAHM MD FRIEDMAN EG TITLEBAUM EL
Citation: Md. Hahm et al., A COMPARISON OF ANALOG AND DIGITAL CIRCUIT IMPLEMENTATIONS OF LOW-POWER MATCHED-FILTERS FOR USE IN PORTABLE WIRELESS COMMUNICATION TERMINALS, IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 44(6), 1997, pp. 498-506
FUNCTIONAL-MODELING OF RSFQ CIRCUITS USING VERILOG HDL
Authors: GAJ K CHEAH CH FRIEDMAN EG FELDMAN MJ
Citation: K. Gaj et al., FUNCTIONAL-MODELING OF RSFQ CIRCUITS USING VERILOG HDL, IEEE transactions on applied superconductivity, 7(2), 1997, pp. 3151-3154
DESIGN AND LOW-SPEED TESTING OF A 4-BIT RSFQ MULTIPLIER-ACCUMULATOR
Authors: HERR QP VUKOVIC N MANCINI CA GAJ K KE Q ADLER V FRIEDMAN EG KRASNIEWSKI A BOCKO MF FELDMAN MJ
Citation: Qp. Herr et al., DESIGN AND LOW-SPEED TESTING OF A 4-BIT RSFQ MULTIPLIER-ACCUMULATOR, IEEE transactions on applied superconductivity, 7(2), 1997, pp. 3168-3171
A CADENCE-BASED DESIGN ENVIRONMENT FOR SINGLE FLUX QUANTUM CIRCUITS
Authors: ADLER V CHEAH CH GAJ K BROCK DK FRIEDMAN EG
Citation: V. Adler et al., A CADENCE-BASED DESIGN ENVIRONMENT FOR SINGLE FLUX QUANTUM CIRCUITS, IEEE transactions on applied superconductivity, 7(2), 1997, pp. 3294-3297
ANALOG DESIGN ISSUES IN DIGITAL VLSI CIRCUITS AND SYSTEMS
Authors: BECERRA JJ FRIEDMAN EG
Citation: Jj. Becerra et Eg. Friedman, ANALOG DESIGN ISSUES IN DIGITAL VLSI CIRCUITS AND SYSTEMS, Analog integrated circuits and signal processing, 14(1-2), 1997, pp. 5-8
DELAY AND POWER EXPRESSIONS FOR A CMOS INVERTER DRIVING A RESISTIVE-CAPACITIVE LOAD
Authors: ADLER V FRIEDMAN EG
Citation: V. Adler et Eg. Friedman, DELAY AND POWER EXPRESSIONS FOR A CMOS INVERTER DRIVING A RESISTIVE-CAPACITIVE LOAD, Analog integrated circuits and signal processing, 14(1-2), 1997, pp. 29-39
RAMP INPUT RESPONSE OF RC TREE NETWORKS
Authors: FRIEDMAN EG MULLIGAN JH
Citation: Eg. Friedman et Jh. Mulligan, RAMP INPUT RESPONSE OF RC TREE NETWORKS, Analog integrated circuits and signal processing, 14(1-2), 1997, pp. 53-58
INCORPORATING INTERCONNECT, REGISTER, AND CLOCK DISTRIBUTION DELAYS INTO THE RETIMING PROCESS
Authors: SOYATA T FRIEDMAN EG MULLIGAN JH
Citation: T. Soyata et al., INCORPORATING INTERCONNECT, REGISTER, AND CLOCK DISTRIBUTION DELAYS INTO THE RETIMING PROCESS, IEEE transactions on computer-aided design of integrated circuits and systems, 16(1), 1997, pp. 105-120
CARE OF THE ADULT WITH PHENYLKETONURIA
Authors: KOCH R AZEN C FRIEDMAN EG FISHLER K BAUMANFRISCHLING C LIN T
Citation: R. Koch et al., CARE OF THE ADULT WITH PHENYLKETONURIA, Journal of investigative medicine, 44(1), 1996, pp. 188-188
DESIGN METHODOLOGY FOR SYNTHESIZING CLOCK DISTRIBUTION NETWORKS EXPLOITING NONZERO LOCALIZED CLOCK SKEW
Authors: NEVES JL FRIEDMAN EG
Citation: Jl. Neves et Eg. Friedman, DESIGN METHODOLOGY FOR SYNTHESIZING CLOCK DISTRIBUTION NETWORKS EXPLOITING NONZERO LOCALIZED CLOCK SKEW, IEEE transactions on very large scale integration (VLSI) systems, 4(2), 1996, pp. 286-291
CARE OF THE ADULT WITH PHENYLKETONURIA
Authors: KOCH R AZEN C FRIEDMAN EG FISHLER K BAUMANNFRISCHLING C LIN T
Citation: R. Koch et al., CARE OF THE ADULT WITH PHENYLKETONURIA, European journal of pediatrics, 155, 1996, pp. 90-92
THE INTERNATIONAL COLLABORATIVE STUDY ON MATERNAL PHENYLKETONURIA - ORGANIZATION, STUDY DESIGN AND DESCRIPTION OF THE SAMPLE
Authors: FRIEDMAN EG KOCH R AZEN C LEVY H HANLEY W MATALON R ROUSE B TREFZ F DELACRUZ F
Citation: Eg. Friedman et al., THE INTERNATIONAL COLLABORATIVE STUDY ON MATERNAL PHENYLKETONURIA - ORGANIZATION, STUDY DESIGN AND DESCRIPTION OF THE SAMPLE, European journal of pediatrics, 155, 1996, pp. 158-161
BROOKEROSE,CHRISTINE AND CONTEMPORARY FICTION - BIRCH,S
Authors: FRIEDMAN EG
Citation: Eg. Friedman, BROOKEROSE,CHRISTINE AND CONTEMPORARY FICTION - BIRCH,S, Modern fiction studies, 42(4), 1996, pp. 893-894
A UNIFIED DESIGN METHODOLOGY FOR CMOS TAPERED BUFFERS
Authors: CHERKAUER BS FRIEDMAN EG
Citation: Bs. Cherkauer et Eg. Friedman, A UNIFIED DESIGN METHODOLOGY FOR CMOS TAPERED BUFFERS, IEEE transactions on very large scale integration (VLSI) systems, 3(1), 1995, pp. 99-111
A CLOCK DISTRIBUTION SCHEME FOR LARGE RSFQ CIRCUITS
Authors: GAJ K FRIEDMAN EG FELDMAN MJ KRASNIEWSKI A
Citation: K. Gaj et al., A CLOCK DISTRIBUTION SCHEME FOR LARGE RSFQ CIRCUITS, IEEE transactions on applied superconductivity, 5(2), 1995, pp. 3320-3324
DESIGN OF TAPERED BUFFERS WITH LOCAL INTERCONNECT CAPACITANCE
Authors: CHERKAUER BS FRIEDMAN EG
Citation: Bs. Cherkauer et Eg. Friedman, DESIGN OF TAPERED BUFFERS WITH LOCAL INTERCONNECT CAPACITANCE, IEEE journal of solid-state circuits, 30(2), 1995, pp. 151-155
THE INTERNATIONAL COLLABORATIVE STUDY OF MATERNAL PHENYLKETONURIA - STATUS-REPORT 1994
Authors: KOCH R LEVY HL MATALON R ROUSE B HANLEY WB TREFZ F AZEN C FRIEDMAN EG DELACRUZ F GUTTLER F ACOSTA PB
Citation: R. Koch et al., THE INTERNATIONAL COLLABORATIVE STUDY OF MATERNAL PHENYLKETONURIA - STATUS-REPORT 1994, Acta paediatrica, 83, 1994, pp. 111-119
LATCHING CHARACTERISTICS OF A CMOS BISTABLE REGISTER
Authors: FRIEDMAN EG
Citation: Eg. Friedman, LATCHING CHARACTERISTICS OF A CMOS BISTABLE REGISTER, IEEE transactions on circuits and systems. 1, Fundamental theory andapplications, 40(12), 1993, pp. 902-908
Risultati: 1-25 | 26-26