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Table of contents of journal: *VLSI design (Print)

Results: 1-25/339
Low power digital multimedia telecommunication designs
Authors: Cho, KS Cho, JD
Citation: Ks. Cho et Jd. Cho, Low power digital multimedia telecommunication designs, VLSI DESIGN, 12(3), 2001, pp. 301-315
Low power design for ASIC cores
Authors: Dean, A Garrett, D Stan, MR Ventrone, S
Citation: A. Dean et al., Low power design for ASIC cores, VLSI DESIGN, 12(3), 2001, pp. 317-331
CADRE: A low-power, low-EMI DSP architecture for digital mobile phones
Authors: Lewis, M Brackenbury, L
Citation: M. Lewis et L. Brackenbury, CADRE: A low-power, low-EMI DSP architecture for digital mobile phones, VLSI DESIGN, 12(3), 2001, pp. 333-348
Exploiting data-dependencies in ultra low-power DSP arithmetic
Authors: Bartlett, VA Grass, E
Citation: Va. Bartlett et E. Grass, Exploiting data-dependencies in ultra low-power DSP arithmetic, VLSI DESIGN, 12(3), 2001, pp. 349-363
A novel low-power shared division and square-root architecture using the GST algorithm
Authors: Kuhlmann, M Parhi, KK
Citation: M. Kuhlmann et Kk. Parhi, A novel low-power shared division and square-root architecture using the GST algorithm, VLSI DESIGN, 12(3), 2001, pp. 365-376
A regularly structured parallel multiplier with low-power non-binary-logiccounter circuits
Authors: Lin, R
Citation: R. Lin, A regularly structured parallel multiplier with low-power non-binary-logiccounter circuits, VLSI DESIGN, 12(3), 2001, pp. 377-390
A low power FIR filter design for image processing
Authors: Jung, JM Chong, JW
Citation: Jm. Jung et Jw. Chong, A low power FIR filter design for image processing, VLSI DESIGN, 12(3), 2001, pp. 391-397
On mixed PTL/static logic for low-power and high-speed circuits
Authors: Cho, GR Chen, T
Citation: Gr. Cho et T. Chen, On mixed PTL/static logic for low-power and high-speed circuits, VLSI DESIGN, 12(3), 2001, pp. 399-406
A low-voltage Floating-Gate MOS biquad
Authors: Rodriguez-Villegas, EO Yufera, A Rueda, A
Citation: Eo. Rodriguez-villegas et al., A low-voltage Floating-Gate MOS biquad, VLSI DESIGN, 12(3), 2001, pp. 407-414
Efficient low power/low swing bus design architectures
Authors: Rjoub, A Koufopavlou, O
Citation: A. Rjoub et O. Koufopavlou, Efficient low power/low swing bus design architectures, VLSI DESIGN, 12(3), 2001, pp. 415-429
Low power built-in self-test schemes for array and booth multipliers
Authors: Bakalis, D Kavousianos, X Vergos, HT Nikolos, D Alexiou, GP
Citation: D. Bakalis et al., Low power built-in self-test schemes for array and booth multipliers, VLSI DESIGN, 12(3), 2001, pp. 431-448
Simultaneous switching noise minimization technique using dual layer powerline mutual inductors
Authors: Lee, Y Choi, J Moon, G Kim, J
Citation: Y. Lee et al., Simultaneous switching noise minimization technique using dual layer powerline mutual inductors, VLSI DESIGN, 12(3), 2001, pp. 449-455
Special issue: Low power architecture and circuit design: Architecture - Preface
Authors: Cho, JD
Citation: Jd. Cho, Special issue: Low power architecture and circuit design: Architecture - Preface, VLSI DESIGN, 12(3), 2001, pp. I-IV
A systematic approach to reduce the system bus load and power in multimedia algorithms
Authors: Danckaert, K Kulkarni, C Catthoor, F De Man, H Tiwari, V
Citation: K. Danckaert et al., A systematic approach to reduce the system bus load and power in multimedia algorithms, VLSI DESIGN, 12(2), 2001, pp. 101-111
Symmetric and programmable Multi-Chip Module for low-power prototyping system
Authors: Yen, MH Chen, SJ Lan, SH
Citation: Mh. Yen et al., Symmetric and programmable Multi-Chip Module for low-power prototyping system, VLSI DESIGN, 12(2), 2001, pp. 113-124
Power optimization of delay constrained circuits
Authors: Nayak, A Haldar, M Banerjee, P Chen, CH Sarrafzadeh, M
Citation: A. Nayak et al., Power optimization of delay constrained circuits, VLSI DESIGN, 12(2), 2001, pp. 125-138
Power-conscious scheduling for real-time embedded systems design
Authors: Shin, Y Choi, K Sakurai, T
Citation: Y. Shin et al., Power-conscious scheduling for real-time embedded systems design, VLSI DESIGN, 12(2), 2001, pp. 139-150
Investigating memory system energy behavior using software and hardware optimizations
Authors: Esakkimuthu, G Kim, HS Kandemir, M Vijaykrishnan, N Irwin, MJ
Citation: G. Esakkimuthu et al., Investigating memory system energy behavior using software and hardware optimizations, VLSI DESIGN, 12(2), 2001, pp. 151-165
Automatic FSM synthesis for low-power mixed synchronous/asynchronous implementation
Authors: Oelmann, B Tammemae, K Kruus, M O'Nils, M
Citation: B. Oelmann et al., Automatic FSM synthesis for low-power mixed synchronous/asynchronous implementation, VLSI DESIGN, 12(2), 2001, pp. 167-186
Accurate power estimation for sequential CMOS circuits using graph-based methods
Authors: Leeser, M Ohm, V
Citation: M. Leeser et V. Ohm, Accurate power estimation for sequential CMOS circuits using graph-based methods, VLSI DESIGN, 12(2), 2001, pp. 187-203
A fast and accurate method of power estimation for logic level networks
Authors: Theodoridis, G Theoharis, S Soudris, D Goutis, C
Citation: G. Theodoridis et al., A fast and accurate method of power estimation for logic level networks, VLSI DESIGN, 12(2), 2001, pp. 205-219
Backward propagated capacitance model for register transfer level power estimation
Authors: Choi, JY Kim, YH Cho, KR
Citation: Jy. Choi et al., Backward propagated capacitance model for register transfer level power estimation, VLSI DESIGN, 12(2), 2001, pp. 221-231
Signal strength based switching activity modeling and estimation for DSP applications
Authors: Chiou, LY Muhammand, K Roy, K
Citation: Ly. Chiou et al., Signal strength based switching activity modeling and estimation for DSP applications, VLSI DESIGN, 12(2), 2001, pp. 233-243
An instruction-level power analysis model with data dependency
Authors: Ascia, G Catania, V Palesi, M Sarta, D
Citation: G. Ascia et al., An instruction-level power analysis model with data dependency, VLSI DESIGN, 12(2), 2001, pp. 245-273
Integrated area-power optimal state assignment
Authors: Tyagi, A
Citation: A. Tyagi, Integrated area-power optimal state assignment, VLSI DESIGN, 12(2), 2001, pp. 275-300
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