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Results: 1-25/37
Authors:
TANG XH
BAIE X
COLINGE JP
Citation: Xh. Tang et al., FABRICATION OF TWIN NANO SILICON WIRES BASED ON ARSENIC DOPANT EFFECT, JPN J A P 1, 37(3B), 1998, pp. 1591-1593
Authors:
BAIE X
COLINGE JP
Citation: X. Baie et Jp. Colinge, 2-DIMENSIONAL CONFINEMENT EFFECTS IN GATE-ALL-AROUND (GAA) MOSFETS, Solid-state electronics, 42(4), 1998, pp. 499-504
Authors:
COLINGE JP
Citation: Jp. Colinge, FULLY-DEPLETED SOI CMOS FOR ANALOG APPLICATIONS, I.E.E.E. transactions on electron devices, 45(5), 1998, pp. 1010-1016
Authors:
RASKIN JP
GILLON R
CHEN J
VANHOENACKERJANVIER D
COLINGE JP
Citation: Jp. Raskin et al., ACCURATE SOI MOSFET CHARACTERIZATION AT MICROWAVE-FREQUENCIES FOR DEVICE PERFORMANCE OPTIMIZATION AND ANALOG MODELING, I.E.E.E. transactions on electron devices, 45(5), 1998, pp. 1017-1025
Authors:
EGGERMONT JP
FLANDRE D
RASKIN JP
COLINGE JP
Citation: Jp. Eggermont et al., POTENTIAL AND MODELING OF 1-MU-M SOI CMOS OPERATIONAL TRANSCONDUCTANCE AMPLIFIERS FOR APPLICATIONS UP TO 1 GHZ, IEEE journal of solid-state circuits, 33(4), 1998, pp. 640-643
Authors:
GENTINNE B
EGGERMONT JP
FLANDRE D
COLINGE JP
Citation: B. Gentinne et al., FULLY DEPLETED SOI-CMOS TECHNOLOGY FOR HIGH-TEMPERATURE IC APPLICATIONS, Materials science & engineering. B, Solid-state materials for advanced technology, 46(1-3), 1997, pp. 1-7
RESEARCH OF HIGH-TEMPERATURE INSTABILITY PROCESSES IN BURIED DIELECTRIC OF FULL DEPLETED SOI MOSFETS
Authors:
NAZAROV AN
COLINGE JP
BARCHUK IP
Citation: An. Nazarov et al., RESEARCH OF HIGH-TEMPERATURE INSTABILITY PROCESSES IN BURIED DIELECTRIC OF FULL DEPLETED SOI MOSFETS, Microelectronic engineering, 36(1-4), 1997, pp. 363-366
Authors:
PAVANELLO MA
MARTINO JA
COLINGE JP
Citation: Ma. Pavanello et al., ANALYTICAL MODELING OF THE SUBSTRATE EFFECT ON ACCUMULATION-MODE SOI PMOSFETS AT ROOM-TEMPERATURE AND AT 77 K, Microelectronic engineering, 36(1-4), 1997, pp. 375-378
Authors:
CHEN J
COLINGE JP
Citation: J. Chen et Jp. Colinge, STUDY ON TITANIUM SALICIDE PROCESS FOR THIN-FILM SOI DEVICES, Microelectronic engineering, 33(1-4), 1997, pp. 189-194
Authors:
PAVANELLO MA
MARTINO JA
COLINGE JP
Citation: Ma. Pavanello et al., ANALYTICAL MODELING OF THE SUBSTRATE INFLUENCES ON ACCUMULATION-MODE SOI PMOSFETS AT ROOM-TEMPERATURE AND AT LIQUID-NITROGEN TEMPERATURE, Solid-state electronics, 41(9), 1997, pp. 1241-1246
Authors:
PAVANELLO MA
MARTINO JA
COLINGE JP
Citation: Ma. Pavanello et al., SUBSTRATE INFLUENCES ON FULLY DEPLETED ENHANCEMENT-MODE SOI MOSFETS AT ROOM-TEMPERATURE AND AT 77 K, Solid-state electronics, 41(1), 1997, pp. 111-119
Authors:
FRANCIS P
COLINGE JP
FLANDRE D
Citation: P. Francis et al., COMPARISON OF SELF-HEATING EFFECT IN GAA AND SOI MOSFETS, Microelectronics and reliability, 37(1), 1997, pp. 61-75
Authors:
BARCHUK IP
KILCHITSKAYA VI
LYSENKO VS
NAZAROV AN
RUDENKO TE
DJURENKO SV
RUDENKO AN
YURCHENKO AP
BALLUTAUD D
COLINGE JP
Citation: Ip. Barchuk et al., ELECTRICAL-PROPERTIES AND RADIATION HARDNESS OF SOI SYSTEMS WITH MULTILAYER BURIED DIELECTRIC, IEEE transactions on nuclear science, 44(6), 1997, pp. 2542-2552
Authors:
BONDARENKO VP
BOGATIREV YV
COLINGE JP
DOLGYI LN
DOROFEEV AM
YAKOVTSEVA VA
Citation: Vp. Bondarenko et al., TOTAL GAMMA-DOSE CHARACTERISTICS OF CMOS DEVICES IN SOI STRUCTURES BASED ON OXIDIZED POROUS SILICON, IEEE transactions on nuclear science, 44(5), 1997, pp. 1719-1723
Authors:
RASKIN JP
VIVIANI A
FLANDRE D
COLINGE JP
Citation: Jp. Raskin et al., SUBSTRATE CROSSTALK REDUCTION USING SOI TECHNOLOGY, I.E.E.E. transactions on electron devices, 44(12), 1997, pp. 2252-2261
Authors:
CHEN J
COLINGE JP
FLANDRE D
GILLON R
RASKIN JP
VANHOENACKER D
Citation: J. Chen et al., COMPARISON OF TISI2, COSI2, AND NISI FOR THIN-FILM SILICON-ON-INSULATOR APPLICATIONS, Journal of the Electrochemical Society, 144(7), 1997, pp. 2437-2442
Authors:
PAVANELLO MA
MARTINO JA
COLINGE JP
Citation: Ma. Pavanello et al., THEORETICAL AND EXPERIMENTAL-STUDY OF THE SUBSTRATE EFFECT ON THE FULLY DEPLETED SOI MOSFET AT LOW-TEMPERATURES, Journal de physique. IV, 6(C3), 1996, pp. 67-72
Authors:
GENTINNE B
FLANDRE D
COLINGE JP
Citation: B. Gentinne et al., MEASUREMENT AND MODELING OF THIN-FILM ACCUMULATION-MODE SOI P-MOSFET INTRINSIC GATE CAPACITANCES, Solid-state electronics, 39(7), 1996, pp. 1071-1078
Authors:
FLANDRE D
FERREIRA LF
JESPERS PGA
COLINGE JP
Citation: D. Flandre et al., MODELING AND APPLICATION OF FULLY DEPLETED SOI MOSFETS FOR LOW-VOLTAGE, LOW-POWER ANALOG CMOS CIRCUITS, Solid-state electronics, 39(4), 1996, pp. 455-460
Authors:
GENTINNE B
FLANDRE D
COLINGE JP
VANDEWIELE F
Citation: B. Gentinne et al., MEASUREMENT AND 2-DIMENSIONAL SIMULATION OF THIN-FILM SOI MOSFETS - INTRINSIC GATE CAPACITANCES AT ELEVATED-TEMPERATURES, Solid-state electronics, 39(11), 1996, pp. 1613-1619
Authors:
COLINGE JP
BAIE X
BAYOT V
GRIVEI E
Citation: Jp. Colinge et al., A SILICON-ON-INSULATOR QUANTUM-WIRE, Solid-state electronics, 39(1), 1996, pp. 49-51
Authors:
EGGERMONT JP
DECEUSTER D
FLANDRE D
GENTINNE B
JESPERS PGA
COLINGE JP
Citation: Jp. Eggermont et al., DESIGN OF SOI CMOS OPERATIONAL-AMPLIFIERS FOR APPLICATIONS UP TO 300-DEGREES-C, IEEE journal of solid-state circuits, 31(2), 1996, pp. 179-186
Authors:
DECEUSTER D
FLANDRE D
COLINGE JP
CRISTOLOVEANU S
Citation: D. Deceuster et al., IMPROVEMENT OF SOI MOS CURRENT-MIRROR PERFORMANCES USING SERIAL-PARALLEL ASSOCIATION OF TRANSISTORS, Electronics Letters, 32(4), 1996, pp. 278-279
Authors:
COLINGE JP
CRAHAY A
DECEUSTER D
DESSARD V
GENTINNE B
Citation: Jp. Colinge et al., IMPROVED LOCOS ISOLATION FOR THIN-FILM SOI MOSFETS, Electronics Letters, 32(19), 1996, pp. 1834-1835
Authors:
CHEN J
COLINGE JP
Citation: J. Chen et Jp. Colinge, TUNGSTEN METALLIZATION TECHNOLOGY FOR HIGH-TEMPERATURE SILICON-ON-INSULATOR DEVICES, Materials science & engineering. B, Solid-state materials for advanced technology, 29(1-3), 1995, pp. 18-20